Interconnect method for implementing scale-up servers

Patent metadata

Field	Value
Publication number	US-2018019953-A1
Application number	US-201615210722-A
Country	US
Kind code	A1
Filing date	Jul 14, 2016
Priority date	Jul 14, 2016
Publication date	Jan 18, 2018
Grant date	—

Abstract

An embodiment includes a first server including a first processor electrically connected to a second processor; a second server including a third processor electrically connected to a fourth processor; a first connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a first connection via the first connection plane and one of the first and second processors is connected to one of the third and fourth processors by a second connection via the first connection plane; and a second connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a third connection via the second connection plane and wherein one of the first and second processors is connected to one of the third and fourth processors by a fourth connection via the second connection plane.

First claim

What is claimed is:

1 . An apparatus for implementing a Symmetric Multi-Processing (“SMP”) system, the apparatus comprising:
a first server including a first processor electrically connected to a second processor;
a second server including a third processor electrically connected to a fourth processor;
a first connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a first connection via the first connection plane and one of the first and second processors is connected to one of the third and fourth processors by a second connection via the first connection plane;
a second connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a third connection via the second connection plane and wherein one of the first and second processors is connected to one of the third and fourth processors by a fourth connection via the second connection plane;
wherein each of the processors of each one of the servers is connected to each of the processors of the other one of the servers.

2 . The apparatus of claim 1 , wherein at least one of the first, second, third, and fourth connections comprises a cache-coherent link.

3 . The apparatus of claim 1 , wherein each of the first, second, third, and fourth connections comprises a cache-coherent link.

4 . The apparatus of claim 1 , wherein the first connection plane comprises a frontplane and the second connection plane comprises at least one of a midplane and a backplane.

5 . The apparatus of claim 1 further comprising a plurality of protocol agnostic electrical redrivers disposed on each of the first and second connection planes, wherein at least one of the first, second, third, and forth connections is made via at least one of the redrivers.

6 . The apparatus of claim 1 , wherein each of the first and second servers comprises a blade server.

7 . The apparatus of claim 1 , wherein the first connection is disposed between the first and third computers, the second connection is disposed between the first and fourth processors, the third connection is disposed between the second and third processors, and the fourth connection is disposed between the second and fourth processors.

8 . The apparatus of claim 1 , wherein the first connection is disposed between the first and third computers, the second connection is disposed between the second and fourth processors, the third connection is disposed between the second and third processors, and the fourth connection is disposed between the first and fourth processors.

9 . An method for implementing a Symmetric Multi-Processing (“SMP”) system, the method comprising:
providing a first server including a first processor electrically connected to a second processor;
providing a second server including a third processor electrically connected to a fourth processor;
providing a first connection plane between the first and second servers;
providing a second connection plane between the first and second servers;
providing a first connection between one of the first and second processors and one of the third and fourth processors via the first connection plane;
providing a second connection between one of the first and second processors and one of the third and fourth processors via the first connection plane;
providing a third connection between one of the first and second processors and one of the third and fourth processors via the second connection plane; and
providing a fourth connection between one of the first and second processors and one of the third and fourth processors via the second connection plane;
wherein each of the processors of each one of the servers is connected to each of the processors of the other one of the servers.

10 . The method of claim 9 , wherein at least one of the first, second, third, and fourth connections comprises a cache-coherent link.

11 . The method of claim 9 , wherein each of the first, second, third, and fourth connections comprises a cache-coherent link.

12 . The method of claim 9 , wherein the first connection plane comprises a frontplane and the second connection plane comprises at least one of a midplane and a backplane.

13 . The method of claim 9 further comprising providing a plurality of redrivers disposed on each of the first and second connection planes, wherein at least one of the first, second, third, and forth connections is made via at least one of the redrivers.

14 . The method of claim 9 , wherein each of the first and second servers comprises a blade server.

15 . The method of claim 9 , wherein the first connection is disposed between the first and third computers, the second connection is disposed between the first and fourth processors, the third connection is disposed between the second and third processors, and the fourth connection is disposed between the second and fourth processors.

16 . The method of claim 9 , wherein the first connection is disposed between the first and third computers, the second connection is disposed between the second and fourth processors, the third connection is disposed between the second and third processors, and the fourth connection is disposed between the first and fourth processors.

17 . An apparatus for implementing a Symmetric Multi-Processing (“SMP”) system, the apparatus comprising:
a first server including a first processor electrically connected to a second processor;
a second server including a third processor electrically connected to a fourth processor;
a third server including a fifth processor electrically connected to a sixth processor;
a fourth server including a seventh processor electrically connected to an eighth processor;
a first connection plane, wherein cache-coherent links are provided between the processors of the first server and the processors of the fourth server via the first connection plane and wherein cache-coherent links are provided between the processors of the second server and the processors of the third server via the first connection plane;
a second connection plane, wherein cache coherent links are provided between the processors of the first server and the processors of the second server via the second connection plane and wherein cache-coherent links are provided between the processors of the third server and the processors of the fourth server via the second connection plane.

18 . The apparatus of claim 17 , wherein the first connection plane comprises a frontplane and the second connection plane comprises at least one of a midplane and a backplane.

19 . The apparatus of claim 17 further comprising a plurality of redrivers disposed on each of the first and second connection planes, wherein the cache coherent links are connected to the first and second connection planes via the redrivers.

20 . The apparatus of claim 17 , wherein the first and second processors are respectively connected to the fourth and third processors via the cache coherent links, the third and fourth processors are respectively connected to the fifth and sixth processors via the cache coherent links, the fifth and sixth processors are respectively connected to the eighth and seventh processors via the cache coherent links, and the seventh and eighth processors are respectively connected to the second and first processors via the cache coherent links.

Assignees

• Cisco Tech Inc

Inventors

• Odisho Victor
• Sen Bidyut Kanti
• Balachandran Jayaprakash
• Leung Michael

Classifications

• H04L67/1095 Primary

  Replication or mirroring of data, e.g. scheduling or transport for data synchronisation between network nodes · CPC title

• H04L67/2842

  Electricity · mapped topic

• H04L47/805 Primary

  QOS or priority aware · CPC title

• H04L67/568 Primary

  Storing data temporarily at an intermediate stage, e.g. caching · CPC title