Integrated photo detector, method of making the same

Patent metadata

Field	Value
Publication number	US-2018019239-A1
Application number	US-201715637889-A
Country	US
Kind code	A1
Filing date	Jun 29, 2017
Priority date	Jul 12, 2016
Publication date	Jan 18, 2018
Grant date	—

Abstract

An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection. The integrated photo detector includes a first photodiode formed in the SOI substrate and associated with a first p-electrode and a first n-electrode. Additionally, the integrated photo detector includes a second photodiode formed in the SOI substrate associated with a second p-electrode and a second n-electrode forming a capacitance no larger than a few femto Faradays. Moreover, the integrated photo detector includes a first electrode and a second electrode disposed respectively on the SOI substrate. The first/second electrode is respectively connected to the first p/n-electrode via a first/second metallic layer patterned with a reduced width from the first/second electrode to the first p/n-electrode and connected to the second p/n-electrode via a first/second metallic wire to make a parallel coupling between the first photodiode and the second photodiode with an ESD threshold of about 100V.

First claim

What is claimed is:

1 . An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection comprising:
an input waveguide formed in a Si-on-insulator (SOI) substrate for receiving a light wave; a first photodiode formed in the SOI substrate and coupled to the input waveguide, the first photodiode being associated with a first p-electrode and a first n-electrode; a second photodiode formed in the SOI substrate associated with a second p-electrode and a second n-electrode forming a capacitance no larger than a few femto Faradays; a first electrode and a second electrode disposed respectively on the SOI substrate, the first electrode being respectively connected to the first p-electrode and the second p-electrode, the second electrode being respectively connected to the first n-electrode and the second n-electrode.

2 . The integrated photo detector of claim 1 , wherein the first photodiode is a Germanium-based photodiode configured to detect the light wave modulated with a high data rate.

3 . The integrated photo detector of claim 1 , wherein the input waveguide comprise a material of silicon or germanium or silicon nitride formed in the SOI substrate for transmitting the light wave therein.

4 . The integrated photo detector of claim 2 , wherein the Germanium-based photodiode comprises a p-type Silicon base patterned within the SOI substrate and an intrinsic Germanium block formed overlying the p-type Silicon base, the p-type Silicon base being partially implanted via a first mask to form a first p++ doped region and the intrinsic Germanium block being partially implanted via a second mask to form a first n++ doped region.

5 . The integrated photo detector of claim 4 , wherein the first p-electrode is physically bounded onto the p++ doped region and the first n-electrode is physically bounded onto the n++ doped region.

6 . The integrated photo detector of claim 1 , wherein the second photodiode is a Silicon-based photodiode coupled to the Germanium-based photodiode to provide an electrostatic discharge damage threshold of ±100V or higher.

7 . The integrated photo detector of claim 6 , wherein the Silicon-based photodiode comprises a p-type Silicon region joined with an n-type Silicon region patterned within the SOI substrate, the p-type Silicon region being partially implanted via a third mask to form a second p++ doped region and the n-type Silicon region being partially implanted via a fourth mask to form a second n++ doped region.

8 . The integrated photo detector of claim 1 , wherein each of the second p-electrode and the second n-electrode is made substantially smaller in size than each of the first p-electrode and the first n-electrode.

9 . The integrated photo detector of claim 2 , wherein each of the first electrode and the second electrode is made substantially larger in size up to a few tens to hundreds of micrometers sufficient for forming a soldering connection with an external digital circuit for outputting an electric signal converted by the Germanium-based photodiode.

10 . The integrated photo detector of claim 9 wherein the electric signal substantially maintains the high data rate of the light wave.

11 . The integrated photo detector of claim 1 , wherein each of the first p-electrode, the second p-electrode, the first n-electrode, the second n-electrode, the first electrode, and the second electrode is formed by patterning a single metallic layer including a first shaped section connected between the first p-electrode and the first electrode, a second shaped section connected between the first n-electrode and the second electrode, a first trace line connected between the second p-electrode and the first electrode, and a second trace line connected between the second n-electrode and the second electrode.

12 . The integrated photo detector of claim 1 , wherein the first/second trace line comprises a width of a few micrometers or less for minimizing the capacitance and yet maintaining electrical connection; the first/second shaped section comprises a reducing width from about hundreds of micrometers of the first/second electrode to a few micrometers of the first p/n-electrode.

13 . An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection comprising:
a Germanium photodiode comprising an intrinsic Germanium layer formed on a p-type Silicon base layer patterned within a Si-on-Insulator (SOI) substrate, the intrinsic Germanium layer comprising a first n++ doped region and the p-type Silicon base layer comprising a first p++ doped region; a Silicon photodiode comprising a Silicon region patterned within the SOI substrate to form a p-type Silicon portion joined with a n-type Silicon portion, the p-type Silicon portion comprising a second p++ doped region and the n-type Silicon portion comprising a second n++ doped region; a first metallic layer being pattered to include a first p-electrode coupled to the first p++ doped region, a second p-electrode coupled to the second p++ doped region, a first electrode connected to the first p-electrode and the second p-electrode; a second metallic layer being pattered to include a first n-electrode coupled to the first n++ doped region, a second n-electrode coupled to the second n++ doped region, a second electrode connected to the first n-electrode and the second n-electrode; wherein the Silicon photodiode is coupled with the Germanium photodiode electrically in parallel with a capacitance of no greater than a few femto Faradays and an enhanced ESD threshold of about ±100V.

14 . The integrated photo detector of claim 13 further comprising a first shaped metallic layer with a reducing width connected from the first electrode to the first p-electrode, a second shaped metallic layer with a reducing width connected from the second electrode to the first n-electrode, a first thin trace line of a few micrometers connected between the first electrode and the second p-electrode, and a second thin trace line of a few micrometers connected between the second electrode and the second n-electrode.

15 . A method for manufacturing an integrated photo detector with improved electrostatic discharge damage (ESD) protection, the method comprising:
forming a first Silicon base block and a second Silicon base block on a substrate; forming a Germanium photodiode partially in the first Silicon base block, the Germanium photodiode being associated with a first p-electrode and a first n-electrode; forming a Silicon photodiode in the second Silicon bask block, the Silicon photodiode being associated with a second p-electrode and a second n-electrode, the second p-electrode and the second n-electrode serving as two terminals of a capacitance no larger than a few femto Faradays; forming a first electrode and a second electrode separately on the substrate; forming a first metallic layer on the substrate to connect the first electrode respectively to the first p-electrode and the second p-electrode, the first metallic layer being patterned to have a first portion with a reducing width connecting the first electrode to the first p-electrode and a second portion with a first trace line connecting the first electrode to the second p-electrode; forming a second metallic layer on the substrate to connect the second electrode respectively to the first n-electrode and the second n-electrode, the second metallic layer being patterned to have a third portion with a reducing width to connect the second electrode to the first n-electrode and a fourth portion with a second trace line to connect the second electrode to the seco

Assignees

• Inphi Corp

Inventors

• Lin Jie
• Kato Masaki

Classifications

• H01L31/02005

  Electricity · mapped topic

• H01L31/1804

  Electricity · mapped topic

• H01L31/103

  Electricity · mapped topic

• H01L27/0248 Primary

  Electricity · mapped topic

• H01L27/1443

  Electricity · mapped topic