Display substrate and manufacturing method thereof, display device and manufacturing method thereof

US2018013079A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2018013079-A1
Application numberUS-201615544727-A
CountryUS
Kind codeA1
Filing dateMar 9, 2016
Priority dateApr 24, 2015
Publication dateJan 11, 2018
Grant date

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Abstract

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The present disclosure provides a display substrate, comprising: a bending resistant region; the region comprises a base and a metal wire layer, wherein the metal wire layer is directly formed on the base, or the region further comprises an organic buffer layer located between the base and the metal wire layer, and the metal wire layer is directly formed on the organic buffer layer. The present disclosure provides a method for manufacturing the display substrate above-described. The present disclosure further provides a display device, comprising the display substrate above-described. The present disclosure further provides a method for manufacturing the display device, comprising the method for manufacturing the display substrate above-described. The present disclosure forms a bending resistant structure in a predetermined bending resistant region on the bezel portions of the display substrate, which can enhance the bend resistance thereof and improve the quality of the flexible display.

First claim

Opening claim text (preview).

1 . A display substrate, comprising a base and a metal wire layer on the base, wherein the display substrate comprises a first region, the base has a first base portion in the first region, and the metal wire layer has a first metal wire layer portion in the first region, and wherein, the first metal wire layer portion is directly formed on the first base portion, or, an organic buffer layer is formed between the first base portion and the first metal wire layer portion, and the first metal wire layer portion is directly formed on the organic buffer layer. 2 . The display substrate according to claim 1 , further comprising a second region adjacent to the first region, wherein the base has a second base portion in the second region, the metal wire layer has a second metal wire layer portion in the second region, and wherein, an inorganic insulating layer is further provided on the second base portion, and the second metal wire layer portion is formed on the inorganic insulating layer. 3 . The display substrate according to claim 1 , wherein, the display substrate further comprises a display region, and the first region is located in bezel regions on both sides of the display region. 4 . The display substrate according to claim 2 , wherein, the inorganic insulating layer comprises an inorganic buffer layer and a gate insulating layer, the metal wire layer is a gate metal layer, and an interlayer insulating layer, a passivation layer, a planarization layer, a pixel defining layer and a packaging layer are sequentially formed on the gate metal layer. 5 . The display substrate according to claim 4 , wherein, the interlayer insulating layer and the passivation layer are discontinuous such that the interlayer insulating layer and the passivation layer are not provided on the first metal wire layer portion. 6 . The display substrate according to claim 2 , wherein, the inorganic insulating layer comprises an inorganic buffer layer, a gate insulating layer and an interlayer insulating layer, the metal wire layer is a source/drain metal layer, and a passivation layer, a planarization layer, a pixel defining layer, and a packaging layer are sequentially formed on the source/drain metal layer. 7 . The display substrate according to claim 6 , wherein, the passivation layer is discontinuous such that no passivation layer is present on the first metal wire layer portion. 8 . The display substrate according to claim 1 , wherein, the first metal wire layer portion is directly formed on the first base portion and a thickness of the first metal wire layer portion is greater than or equal to a thickness of the second metal wire layer portion such that the upper surface of the metal wire layer is flat. 9 . The display substrate according to claim 1 , wherein, the base comprises at least one of polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate. 10 . The display substrate according to claim 4 or 6 , wherein, the packaging layer is formed by alternately depositing a plurality of inorganic layers and organic layers. 11 . A method for manufacturing a display substrate, comprising: providing a base; forming a metal wire layer on the base, such that: a first metal wire layer portion of the metal wire layer is directly formed on a first base portion of the base, or, an organic buffer layer is provided between a first metal wire layer portion of the metal wire layer and a first base portion of the base, and the first metal wire layer portion is directly provided on the organic buffer layer. 12 . The method according to claim 11 , wherein, the base further has a second base portion, the method further comprising: providing an inorganic insulating layer only on the second base portion such that the inorganic insulating layer is provided between the second base portion of the base and the second metal wire layer portion of the metal wire layer. 13 . The method according to claim 11 , wherein, the base further has a second base portion, the method further comprising: forming an inorganic insulating layer on the first base portion and the second base portion; removing the inorganic insulating layer on the first base portion. 14 . The method according to claim 12 , wherein, the inorganic insulating layer comprises an inorganic buffer layer and a gate insulating layer, the metal wire layer being a gate metal layer, the method further comprising: sequentially forming an interlayer insulating layer, a passivation layer, a planarization layer, a pixel defining layer and a packaging layer on the gate metal layer. 15 . The method according to claim 14 , wherein, the interlayer insulating layer and the passivation layer are discontinuous such that the interlayer insulating layer and the passivation layer are not provided on the first metal wire layer portion. 16 . The method according to claim 12 , wherein, the inorganic insulating layer comprises an inorganic buffer layer, a gate insulating layer and an interlayer insulating layer, the metal wire layer being a source/drain metal layer, the method further comprising: sequentially forming a passivation layer, a planarization layer, a pixel defining layer and a packaging layer on the source/drain metal layer. 17 . The method according to claim 16 , wherein, the passivation layer is discontinuous such that no passivation layer is present on the first metal wire layer portion. 18 . The method according to claim 14 or 16 , wherein, forming the packaging layer comprises: alternately depositing a plurality of inorganic layers and organic layers to form the packaging layer. 19 . A display device comprising the display substrate according to claim 1 . 20 . A method for manufacturing a display device, comprising a method for manufacturing a display substrate according to claim 11 .

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What does patent US2018013079A1 cover?
The present disclosure provides a display substrate, comprising: a bending resistant region; the region comprises a base and a metal wire layer, wherein the metal wire layer is directly formed on the base, or the region further comprises an organic buffer layer located between the base and the metal wire layer, and the metal wire layer is directly formed on the organic buffer layer. The present…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L51/0097. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jan 11 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).