Methods of forming semiconductor devices
US-2024387699-A1 · Nov 21, 2024 · US
Method of planarizing substrate surface
US2018012772A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2018012772-A1 |
| Application number | US-201715678134-A |
| Country | US |
| Kind code | A1 |
| Filing date | Aug 16, 2017 |
| Priority date | Jul 5, 2016 |
| Publication date | Jan 11, 2018 |
| Grant date | — |
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- Title
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Abstract
Official abstract text for this publication.
A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.
First claim
Opening claim text (preview).
What is claimed is: 1 . A method of planarizing a substrate surface, comprising: providing a substrate having a major surface of a material layer, wherein the major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate; depositing a polish stop layer on the major surface of the material layer; forming a photoresist pattern on the polish stop layer, wherein the photoresist pattern masks the second region of relatively high removal rate, while exposes at least a portion of the first region with relatively low removal rate; etching away at least a portion of the polish stop layer not covered by the photoresist pattern; and removing the photoresist pattern. 2 . The method according to claim 1 , wherein after removing the photoresist pattern, the method further comprises: depositing a cap layer on the polish stop layer and on the material layer; and performing a chemical mechanical polishing (CMP) process to polish the cap layer. 3 . The method according to claim 2 , wherein the material layer comprises amorphous silicon. 4 . The method according to claim 2 , wherein the CMP process stops on the polish stop layer. 5 . The method according to claim 4 , wherein the polish stop layer comprises silicon nitride, and wherein the cap layer comprises silicon oxide or amorphous silicon. 6 . The method according to claim 2 , wherein after performing the CMP process to polish the cap layer and the material layer, the method further comprises: performing a dry etching process to etch the polishing stop layer and the material layer.
Assignees
Inventors
Classifications
the removal being chemical etching · CPC title
- H10P95/062Primary
involving a dielectric removal step · CPC title
Electricity · mapped topic
Electricity · mapped topic
- H01L21/31053Primary
Electricity · mapped topic
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- What does patent US2018012772A1 cover?
- A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at…
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10P95/062. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Jan 11 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).