Solid state drive

Patent metadata

Field	Value
Publication number	US-2018011663-A1
Application number	US-201715640907-A
Country	US
Kind code	A1
Filing date	Jul 3, 2017
Priority date	Jul 5, 2016
Publication date	Jan 11, 2018
Grant date	—

Abstract

A memory stores data, a memory interface circuit reads the data from the memory, and an arithmetic circuit performs a prescribed arithmetic operation on the data. A host interface circuit outputs an arithmetic request to the arithmetic circuit, and also outputs a reading instruction to the memory via the memory interface circuit, upon receipt of an arithmetic instruction from a host device. The host interface circuit receives, from the arithmetic circuit, an arithmetic result of the prescribed arithmetic operation performed on the data read from the memory via the memory interface circuit, and outputs the arithmetic result to the host device.

First claim

What is claimed is:

1 . A solid state drive comprising:
a memory that stores data; a memory interface circuit that reads the data from the memory; an arithmetic circuit that performs a prescribed arithmetic operation on the data; and a host interface circuit that outputs an arithmetic request to the arithmetic circuit, and also outputs a reading instruction to the memory via the memory interface circuit, upon receipt of an arithmetic instruction from a host device, that receives, from the arithmetic circuit, an arithmetic result of the prescribed arithmetic operation performed on the data read from the memory via the memory interface circuit, and that outputs the arithmetic result to the host device.

2 . The solid state drive according to claim 1 , wherein
the reading instruction is an instruction that specifies the arithmetic circuit to be a transfer destination of the data read from the memory, and the memory interface circuit transfers the data read from the memory to the arithmetic circuit.

3 . The solid state drive according to claim 1 , wherein
the arithmetic circuit includes a plurality of individual arithmetic circuits that respectively perform plural different arithmetic operations, and the host interface circuit outputs the arithmetic request to a specific individual arithmetic circuit that performs the prescribed arithmetic operation that corresponds to the arithmetic instruction from among the plurality of individual arithmetic circuits, and receives the arithmetic result from the specific individual arithmetic circuit.

4 . The solid state drive according to claim 1 , wherein
the arithmetic instruction is a search instruction including a search target, the prescribed arithmetic operation is an arithmetic operation to compare the data read from the memory with the search target, and the arithmetic result indicates whether the search target is included in the data read from the memory.

5 . The solid state drive according to claim 1 , wherein
the arithmetic instruction is an arithmetic instruction to request a statistical value, the prescribed arithmetic operation is an arithmetic operation to calculate the statistical value of the data read from the memory, and the arithmetic result includes the statistical value calculated by the arithmetic circuit.

Assignees

• Fujitsu Ltd

Inventors

• Kuwamura Shinya

Classifications

• G06F9/3004

  to perform operations on memory · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0611

  in relation to response time · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title