Computer system and method for controlling operating frequency of processor

Patent metadata

Field	Value
Publication number	US-2018004549-A1
Application number	US-201615225645-A
Country	US
Kind code	A1
Filing date	Aug 1, 2016
Priority date	Jul 1, 2016
Publication date	Jan 4, 2018
Grant date	—

Abstract

A computer system including a PCH (platform controller hub), a CPLD (complex programmable logic device), a first switch and a processor, and a control method are provided to control the operation frequency of the processor. The CPLD is coupled to the PCH and the first switch. The processor is coupled to the first switch. The PCH produces and outputs a second control signal according to the first firmware and a first control signal from a command input unit. The CPLD produces and outputs a third control signal according to the second firmware and the second control signal. The first switch receives the third control signal and is turned on to output a triggering signal when the third control signal is valid. The processor includes a PROCHOT pin. The processor receives the triggering signal and triggers the PROCHOT pin for frequency control.

First claim

What is claimed is:

1 . A computer system of controlling a operating frequency of a processor, comprising:
a platform controller hub configured to receive a first control signal of a command input unit, and generate and output a second control signal according to first firmware and the first control signal; a complex programmable logic device coupled to the platform controller hub and configured to receive the second control signal and generate and output a third control signal according to second firmware and the second control signal; a first switch coupled to the complex programmable logic device and configured to receive the third control signal, and be turned on to output a triggering signal when the third control signal is a valid signal; and the processor comprising a PROCHOT pin, the processor coupled to the first switch and configured to receive the triggering signal to trigger the PROCHOT pin to carry out frequency control.

2 . The computer system according to claim 1 , wherein the first switch comprises a first end, a second end and a control end, the first end is coupled to a ground end, the second end is coupled to the PROCHOT pin, and the control end is coupled to the complex programmable logic device.

3 . The computer system according to claim 1 , wherein the third control signal is a voltage potential signal, and when the voltage potential signal is low, the complex programmable logic device turns on the first switch.

4 . The computer system according to claim 1 , wherein the command input unit is an external command input device that is pluggable and coupled to the platform controller hub.

5 . The computer system according to claim 1 , wherein the second control signal is a SGPIO signal, the second firmware comprises a second control command that is executable according to the second control signal to generate and output the third control signal.

6 . The computer system according to claim 1 , wherein the PROCHOT pin is predeterminedly at a high voltage potential.

7 . A method of controlling a operating frequency of a processor, comprising:
providing a first control signal to a platform controller hub; making the platform controller hub receive the first control signal and generate and output a second control signal according to first firmware and the first control signal; making a complex programmable logic device receive the second control signal and generate and output a third control signal according to second firmware and the second control signal; making a first switch receive the third control signal, and determining whether the third control signal is valid, and turning on the first switch to output a triggering signal when the third control signal is valid; and making a PROCHOT pin of the processor receive the triggering signal so that the PROCHOT pin is triggered to carry out frequency control.

8 . The method according to claim 7 , wherein the third control signal is a voltage potential signal, and when the voltage potential signal is low, the first switch is turned on by the complex programmable logic device.

9 . The method according to claim 7 , wherein the second control signal is a SGPIO signal, the second firmware comprises a second control command, and the third control signal is generate and outputted when the second control command is executed according to the second control signal.

10 . The method according to claim 7 , wherein the PROCHOT pin is predeterminedly at a high voltage potential.

Assignees

• Inventec (Pudong) Tech Corporation
• Inventec Corp

Inventors

• Han ying-xian

Classifications

• G06F1/206 Primary

  comprising thermal management · CPC title

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F9/44505 Primary

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/324

  by lowering clock frequency · CPC title