Microcontroller for memory management unit

Patent metadata

Field	Value
Publication number	US-2017371802-A9
Application number	US-201314011643-A
Country	US
Kind code	A9
Filing date	Aug 27, 2013
Priority date	Mar 15, 2013
Publication date	Dec 28, 2017
Grant date	—

Abstract

One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

First claim

What is claimed is:

1 . A system configured to perform virtual memory operations, the system comprising:
a first memory that includes a page table having a plurality of page table entries; a memory management unit coupled to the first memory and configured to:
process requests for translating virtual memory addresses to physical memory addresses, and
manage the plurality of page table entries;
a microcontroller coupled to the memory management unit and configured to perform one or more operations related to remedying a page fault generated by the memory management unit; and a parallel processing unit coupled to the first memory, the memory management unit, and the microcontroller.

2 . The system of claim 1 , wherein the page fault is associated with a reserved zero-filled page included in the first memory.

3 . The system of claim 2 , wherein the one or more operations comprise:
receiving the page fault, wherein the page fault is associated with a write attempt via a first virtual memory address; determining that the first virtual memory address is mapped to the reserved zero-filled page; selecting a first memory page, wherein no virtual memory address is mapped to the first memory page, and every entry included in the first memory page has a value of binary zero; updating a first page table entry included in the plurality of page table entries to map the first virtual memory address to the first memory page; and activating both a read permission bit and a write permission bit included in the first page table entry.

4 . The system of claim 3 , wherein the one or more operations further comprise deactivating a status of zero-fill-on-demand in a state entry that is associated with the first virtual memory address.

5 . The system of claim 4 , wherein the state entry is included in a page state directory included in a second physical memory.

6 . The system of claim 2 , wherein the one or more operations comprise:
receiving the page fault, wherein the page fault is associated with a write attempt via a first virtual memory address; determining that the first virtual memory address is mapped to the reserved zero-filled page; allocating a first memory page; setting every entry included in the first memory page to a value of binary zero. updating a first page table entry included in the plurality of page table entries to map the first virtual memory address to the first memory page; and activating both a read permission bit and a write permission bit included in the first page table entry.

7 . The system of claim 1 , wherein the page fault is associated with a copy-on-write page included in the first memory.

8 . The system of claim 7 , wherein the one or more operations comprise:
receiving the page fault, wherein the page fault is associated with a write attempt via a first virtual memory address; determining that the first virtual memory address is mapped to the copy-on-write page; selecting a first memory page, wherein no virtual memory address is mapped to the first memory page; copying the copy-on-write page to the first memory page; updating a first page table entry included in the plurality of page table entries to map the first virtual memory address to the first memory page; and activating both a read permission bit and a write permission bit included in the first page table entry.

9 . The system of claim 8 , wherein the one or more operations further comprise:
determining that only one virtual memory address is mapped to the copy-on-write page; and deactivating a status of copy-on-write in a state entry that is associated with the copy-on-write page.

10 . The system of claim 9 , wherein the state entry is included in a page state directory included in a second physical memory.

11 . The system of claim 1 , wherein the page fault is associated with a first virtual memory address that is not associated with any page table entries included in the plurality of page table entries.

12 . The system of claim 11 , wherein the one or more operations comprise updating a first page table entry included in the plurality of page table entries to map the first virtual memory address to a first memory page included in a second memory.

13 . A computing device, comprising:
a first memory that includes a page table having a plurality of page table entries; a memory management unit configured to:
process requests for translating virtual memory addresses to physical memory addresses, and
manage the plurality of page table entries;
a microcontroller configured to:
perform one or more operations related to remedying a page fault generated by the memory management unit, and
a parallel processing unit.

14 . The computing device of claim 13 , wherein the one or more operations comprise:
receiving the page fault, wherein the page fault is associated with a write attempt via a first virtual memory address; determining that the first virtual memory address is mapped to a reserved zero-filled page; selecting a first memory page, wherein no virtual memory address is mapped to the first memory page, and every entry included in the first memory page has a value of binary zero; updating a first page table entry included in the plurality of page table entries to map the first virtual memory address to the first memory page; and activating both a read permission bit and a write permission bit included in the first page table entry.

15 . The computing device of claim 13 , wherein the one or more operations comprise:
receiving the page fault, wherein the page fault is associated with a write attempt via a first virtual memory address; determining that the first virtual memory address is mapped to a copy-on-write page; selecting a first memory page, wherein no virtual memory address is mapped to the first memory page; copying the copy-on-write page to the first memory page; updating a first page table entry included in the plurality of page table entries to map the first virtual memory address to the first memory page; and activating both a read permission bit and a write permission bit included in the first page table entry.

16 . The computing device of claim 13 , wherein the one or more operations comprise:
receiving the page fault, wherein the page fault is associated with a first virtual memory address that is not associated with any page table entries included in the plurality of page table; and updating a first page table entry included in the plurality of page table entries to map the first virtual memory address to a first memory page included in a second memory.

17 . A computer-implemented method for performing virtual memory operations, the method comprising:
receiving a page fault associated with a first virtual memory address; and performing one or more operations related to remedying the page fault.

18 . The method of claim 17 , wherein the one or more operations comprise:
determining that the first virtual memory address is mapped to a reserved zero-filled page; selecting a first memory page, wherein no virtual memory address is mapped to the first memory page, and every entry included in the first memory page has a value of binary zero; updating a first page table entry included in a page table to map the first virtual memory address to the first memory page; activating both a read permission bit and a write permission bit included in the first page table entry.

19 . The method of claim 17 , wherein the one or more operations comprise:
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Assignees

• Nvidia Corp

Inventors

• Buschardt Cameron
• Duluk Jr Jerome F
• Mashey John
• Hairgrove Mark
• Deming James Leroy
• Fahs Brian

Classifications

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/10

  Address translation · CPC title

• G06F2212/684

  TLB miss handling · CPC title

• G06F2212/301

  In special purpose processing node, e.g. vector processor · CPC title