Global capabilities transferrable across node boundaries

US2017371663A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017371663-A1
Application numberUS-201615192742-A
CountryUS
Kind codeA1
Filing dateJun 24, 2016
Priority dateJun 24, 2016
Publication dateDec 28, 2017
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

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Example implementations relate to global capabilities transferrable across node boundaries. For example, in an implementation, a switch that routes traffic between a node and global memory may receive an instruction from the node. The switch may recognize that data referenced by the instruction is a global capability, and the switch may process that global capability accordingly.

First claim

Opening claim text (preview).

What is claimed: 1 . A system comprising: global memory; a node that includes a processing resource; and a switch that routes traffic between the node and the global memory, the switch to: receive from the node an instruction to read or write data, recognize that the received instruction relates to a global capability transferrable across node boundaries and that the data forms at least part of the global capability, and in response to recognition that the received instruction relates to the global capability, process the instruction at the global memory using the global capability according to global capability metadata of the global capability. 2 . The system of claim 1 , wherein the switch is to recognize that the received instruction relates to a global capability by detection of a global capability tag set in the data by determination that the instruction is a global capability instruction. 3 . The system of claim 1 , wherein the instruction received from the node is an instruction to write data, the switch is to process the instruction by: a write of the data as the global capability into a specialized memory, the data as received from the node having a node-generated global capability tag, or if the instruction is a global capability instruction, passage of the instruction to a media controller that services the specialized memory for processing, the processing including generation of a media controller-generated global capability tag and a write of the data and the media controller-generated global capability tag as the global capability into the specialized memory, and the specialized memory is a memory separate from the global memory or is a special address range of the global memory. 4 . The system of claim 3 , wherein the switch is to initialize a region of the global memory when the global capability is written, in response to initialization being specified in the global capability metadata. 5 . The system of claim 3 , wherein the switch is to open a mapping between a region of the global memory and the node, in response to the mapping being specified in the global capability metadata. 6 . The system of claim 1 , wherein the instruction received from the node is to read data, the node is among a plurality of nodes, the global capability metadata indicates which nodes of the plurality are included in a trusted partition associated with the global capability, and the switch is included in a fabric that couples the plurality of nodes to the global memory, and the switch is to process the instruction by: determination from the global capability metadata of whether the node is in the trusted partition, and if the node is determined to be in the trusted partition, transmission to the node of the global capability. 7 . The system of claim 1 , wherein the global capability metadata indicates a switch programming command, and the switch processes the instruction according to the global capability metadata by execution of the switch programming command. 8 . The system of claim 7 , wherein the switch programming command is to control a firewall of the switch, to restart the switch, to read a state of the switch, to revoke access to global capabilities, or to access debugging information of the switch. 9 . The system of claim 1 , further comprising an out-of-band hardware module to provide a trusted initial set of capabilities to the node. 10 . A method comprising: receiving, by a switch that couples a plurality of nodes to global memory, an instruction to read or write data, the instruction originating from a node of the plurality; detecting, by the switch, that the data includes a set global capability tag or that the received instruction is a global capability instruction; in response to the detecting, recognizing, by the switch, the data as a global capability transferrable across node boundaries; and processing, by the switch and at the global memory, the instruction using the global capability according to global capability metadata included in the global capability. 11 . The method of claim 10 , wherein the instruction is to write data, and the processing includes the switch cooperating with a media controller to: write the global capability, including the global capability tag and global capability metadata, to a specialized memory, or pass the instruction that is a global capability instruction to the media controller for handling that includes generation of a media controller-generated global capability tag. 12 . The method of claim 10 , wherein the instruction is to read data, the global capability metadata indicates which nodes of the plurality are included in a trusted partition associated with the global capability, and the processing includes: determining from the global capability metadata whether the node from which the instruction is received is in the trusted partition, and if the node is determined to be in the trusted partition, transmitting to the node the global capability. 13 . The method of claim 10 , wherein the processing includes: determining, by the switch, that the global capability addresses the switch and that the global capability metadata indicates a switch programming command, and executing, by the switch, the switch programming command. 14 . A non-transitory machine readable medium storing instructions executable by a processing resource of a switch that couples a plurality of nodes to global memory, the non-transitory machine readable medium comprising: instructions to receive, from a node of a plurality of nodes, a node instruction to read or write data; instructions to determine that either the data includes a set global capability tag or that the node instruction is a global capability instruction, and the data is therefore a global capability transferrable across node boundaries; instructions to analyze global capability metadata included in the global capability; instructions to, if the node instruction is to write, cooperate with a media controller to write the global capability to a specialized memory; and instructions to, if the node instruction is to read, transmit to the node the global capability from the specialized memory upon determination that the node is included in a trusted partition specified by the global capability metadata. 15 . The non-transitory machine readable medium of claim 14 , further comprising: instructions to execute a switch programming command included in the global capability; instructions to initialize a region of the global memory as specified by the global capability metadata; and instructions to open a mapping of a region of the global memory into the node as specified by the global capability metadata.

Assignees

Inventors

Classifications

  • Details of memory controller · CPC title

  • User address space allocation, e.g. contiguous or non contiguous base addressing · CPC title

  • Distributed memory · CPC title

  • Instruction analysis, e.g. decoding, instruction word fields · CPC title

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Frequently asked questions

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What does patent US2017371663A1 cover?
Example implementations relate to global capabilities transferrable across node boundaries. For example, in an implementation, a switch that routes traffic between a node and global memory may receive an instruction from the node. The switch may recognize that data referenced by the instruction is a global capability, and the switch may process that global capability accordingly.
Who is the assignee on this patent?
Hewlett Packard Entpr Dev Lp
What technology area does this patent fall under?
Primary CPC classification G06F13/1668. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Dec 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).