Compression/decompression apparatus, storage system, and compression/decompression method
US-2024088919-A1 · Mar 14, 2024 · US
US2017366199A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2017366199-A1 |
| Application number | US-201715611201-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jun 1, 2017 |
| Priority date | Jun 17, 2016 |
| Publication date | Dec 21, 2017 |
| Grant date | — |
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A first error-detecting code (EDC) is computed based on a first segment of a block of information that is to be encoded, and a second EDC is computed based on at least a second segment of the block of information. The first EDC is masked with a first masking segment and the second EDC with a second masking segment to generate a first masked EDC and a second masked EDC. The first masking segment and the second masking segment are associated with a target receiver of the block of information. A codeword is generated based on a code and an input vector that includes the first segment, the first masked EDC, the second segment, and the second masked EDC. This type of coding could be useful to support early termination of blind detection at a decoder, for example.
Opening claim text (preview).
1 . An apparatus comprising: an encoder to compute a first error-detecting code (EDC) based on a first segment of a block of information that is to be encoded and a second EDC based on at least a second segment of the block of information, to mask the first EDC with a first masking segment and the second EDC with a second masking segment to generate a first masked EDC and a second masked EDC, the first masking segment and the second masking segment being associated with a target receiver of the block of information, and to generate a codeword based on a code and an input vector that includes the first segment, the first masked EDC, the second segment, and the second masked EDC; a transmitter, coupled to the encoder, to transmit the codeword. 2 . The apparatus of claim 1 , wherein the code is a polar code. 3 . The apparatus of claim 1 , wherein the first EDC and the second EDC are cyclic redundancy check (CRC) codes, checksum codes, or Fletcher codes. 4 . The apparatus of claim 1 , wherein the encoder is configured to compute the second EDC based on the first segment, the first EDC, and the second segment. 5 . The apparatus of claim 1 , wherein the first segment has a length m 1 , the second segment has a length m 2 , and m 1 is different from m 2 . 6 . The apparatus of claim 1 , wherein the first EDC has a length p 1 , the second EDC has a length p 2 , and p 1 is different from p 2 . 7 . The apparatus of claim 1 , wherein the first masking segment and the second masking segment are based on an identifier associated with the target receiver. 8 . The apparatus of claim 7 , wherein the identifier is a Radio Network Temporary Identifier (RNTI). 9 . The apparatus of claim 7 , wherein the first masking segment comprises a first part of the identifier, and the second masking segment comprises a second part of the identifier. 10 . The apparatus of claim 1 , wherein the encoder is further configured to, for each of at least one further segment that follows the second segment in the block of information: compute a further EDC based on at least the further segment; and mask the further EDC with a further masking segment that is associated with the target receiver to generate a further masked EDC, wherein the input vector includes the first segment, the first masked EDC, the second segment, the second masked EDC, each further segment, and each further masked EDC. 11 . User equipment comprising the apparatus of claim 1 . 12 . Communication network equipment comprising the apparatus of claim 1 . 13 . A method comprising: computing a first error-detecting code (EDC) based on a first segment of a block of information that is to be encoded and a second EDC based on at least a second segment of the block of information; masking the first EDC with a first masking segment and the second EDC with a second masking segment to generate a first masked EDC and a second masked EDC, the first masking segment and the second masking segment being associated with a target receiver of the block of information; generating a codeword based on a code and an input vector that includes the first segment, the first masked EDC, the second segment, and the second masked EDC; and transmitting the codeword. 14 . The method of claim 13 , wherein the code is a polar code. 15 . The method of claim 13 , wherein the first EDC and the second EDC are cyclic redundancy check (CRC) codes, checksum codes, or Fletcher codes. 16 . The method of claim 13 , wherein the computing comprises computing the second EDC based on the first segment, the first EDC, and the second segment. 17 . The method of claim 13 , wherein the first segment has a length m 1 , the second segment has a length m 2 , and m 1 is different from m 2 . 18 . The method of claim 13 , wherein the first EDC has a length p 1 , the second EDC has a length p 2 , and p 1 is different from p 2 . 19 . The method of claim 13 , wherein the first masking segment and the second masking segment are based on an identifier associated with the target receiver. 20 . The method of claim 19 , wherein the identifier is a Radio Network Temporary Identifier (RNTI). 21 . The method of claim 19 , wherein the first masking segment comprises a first part of the identifier, and the second masking segment comprises a second part of the identifier. 22 . The method of claim 13 , further comprising, for each of at least one further segment that follows the second segment in the block of information: computing a further EDC based on at least the further segment; and masking the further EDC with a further masking segment that is associated with the target receiver to generate a further masked EDC, wherein the input vector includes the first segment, the first masked EDC, the second segment, the second masked EDC, each further segment, and each further masked EDC. 23 . A non-transitory processor-readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform a method comprising: computing a first error-detecting code (EDC) based on a first segment of a block of information that is to be encoded and a second EDC based on at least a second segment of the block of information; masking the first EDC with a first masking segment and the second EDC with a second masking segment to generate a first masked EDC and a second masked EDC, the first masking segment and the second masking segment being associated with a target receiver of the block of information; generating a codeword based on a code and an input vector that includes the first segment, the first masked EDC, the second segment, and the second masked EDC; and transmitting the codeword.
to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title
Generic software techniques for error detection or fault masking · CPC title
Arrangements at the receiver end · CPC title
Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms · CPC title
Linear codes · CPC title
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