Integrated circuit and method of testing

Patent metadata

Field	Value
Publication number	US-2017366177-A1
Application number	US-201715693848-A
Country	US
Kind code	A1
Filing date	Sep 1, 2017
Priority date	Sep 25, 2014
Publication date	Dec 21, 2017
Grant date	—

Abstract

An integrated circuit for testing a circuit includes a controller configured to select a loopback path of the circuit. The circuit includes a data path and an inverter, and each is electrically coupled to the selected loopback path. The integrated circuit includes a counter electrically coupled to the selected loopback path. The circuit is configured to receive a first voltage signal that is either a substantially low logic level signal or a substantially high logic level signal. The circuit is configured to generate an oscillating signal from the first voltage signal, and the counter is configured to count oscillations of the oscillating signal.

First claim

What is claimed is:

1 . A method of testing a circuit, the method comprising:
electrically connecting a test circuit to the circuit; selecting a loopback path from a plurality of loopback paths in the circuit, wherein a data path of the circuit is electrically coupled to the selected loopback path; receiving a first voltage signal, wherein the first voltage signal is a substantially low logical level signal or a substantially high logical level signal; generating a second voltage signal from the first voltage signal, wherein the first voltage signal is applied to the data path, and wherein the second voltage signal oscillates between the substantially low logical level and the substantially high logical level at an oscillation frequency; and measuring the oscillation frequency of the second voltage signal.

2 . The method of claim 1 , wherein measuring the oscillation frequency of the second voltage signal comprises counting oscillations of the second voltage signal.

3 . The method of claim 2 , further comprising:
receiving a time period of a counter, wherein the time period is a duration of counting oscillations of the second voltage signal.

4 . The method of claim 3 , further comprising:
resetting the counter responsive to receipt of a reset control signal.

5 . The method of claim 1 , further comprising:
electrically connecting the selected loopback path of the plurality of loopback paths to a counter.

6 . The method of claim 5 , further comprising:
electrically disconnecting from the counter, an unselected loopback path.

7 . The method of claim 1 , further comprising:
selectively enabling a first inverter of the circuit and, substantially concurrently, disabling a second inverter of the circuit.

8 . The method of claim 1 , further comprising:
inverting the first voltage signal; applying the inverted first voltage signal to a flip-flop circuit; and inverting the inverted first voltage signal.

9 . The method of claim 1 , further comprising:
sending a first control signal and a second control signal to the circuit; enabling the selected loopback path based on a state of the first control signal; and disabling an unselected loopback path based on a state of the second control signal.

10 . An integrated circuit for testing a circuit, the integrated circuit comprising:
a first circuit comprising a loopback path electrically coupled to an inverter; and a test circuit comprising a controller and a counter, wherein the test circuit is electrically coupled to the first circuit, and wherein the controller is configured to select the loopback path, wherein
the first circuit is configured to:
receive a first voltage signal, wherein the first voltage signal is either a substantially low logic level signal or a substantially high logic level signal, and
generate an oscillating signal from the received first voltage signal, and the counter is configured to count oscillations of the oscillating signal.

11 . The integrated circuit of claim 10 , further comprising:
a second circuit having a plurality of input terminals electrically coupled to the first circuit, and an output terminal electrically coupled to the counter.

12 . The integrated circuit of claim 10 , wherein the test circuit further comprises an encoder electrically coupled to an output terminal of the controller; and
an interface electrically coupled to an input terminal of the controller.

13 . The integrated circuit of claim 10 , wherein the first circuit further comprises a first flip-flop circuit having an input terminal configured to receive the first voltage signal.

14 . The integrated circuit of claim 13 , wherein the first circuit further comprises a second flip-flop circuit having an input terminal configured to receive a second voltage signal, wherein the second voltage signal is an inversion of the first voltage signal.

15 . The integrated circuit of claim 10 , wherein the counter comprises a ripple counter electrically coupled to the controller and configured to receive a reset control signal and a time period control signal from the controller.

16 . A test circuit, comprising:
a controller electrically coupled to a first circuit, and configured to activate a first feedback path of the first circuit, disable a second feedback path of the first circuit, and output a first voltage signal, wherein the first voltage signal is either a substantially low logic level signal or a substantially high logic level signal; a frequency counter electrically coupled to the controller and configured to receive a second voltage signal from the first circuit, wherein the second voltage signal is derived from the first voltage signal; an interface electrically coupled to the controller and the frequency counter, wherein the interface is configured to receive a counter output signal from the frequency counter; and an output pad electrically coupled to an output terminal of the interface, and configured to receive a measured oscillation frequency of the first circuit.

17 . The test circuit of claim 16 , wherein the frequency counter is configured to count oscillations of the second voltage signal for a duration derived from a time period control signal received at an input pad of the test circuit.

18 . The test circuit of claim 17 , wherein the test circuit is configured to reset the frequency counter based on a reset control signal received at the input pad of the test circuit.

19 . The test circuit of claim 16 , further comprising:
a ring output pad; and a multiplexer electrically coupled to the ring output pad and the frequency counter.

20 . The test circuit of claim 16 , further comprising:
a second circuit electrically coupled to the controller, and configured to receive the first voltage signal from the controller and output to the first circuit the first voltage signal and at least one feedback path activation signal.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chien Jinn-Yeh

Classifications

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• H03K5/26 Primary

  the characteristic being duration, interval, position, frequency, or sequence · CPC title