Semiconductor device assembly with heat transfer structure formed from semiconductor material

Patent metadata

Field	Value
Publication number	US-2017365584-A1
Application number	US-201715693750-A
Country	US
Kind code	A1
Filing date	Sep 1, 2017
Priority date	May 19, 2015
Publication date	Dec 21, 2017
Grant date	—

Abstract

Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.

First claim

I/we claim:

1 . A semiconductor device assembly, comprising:
a semiconductor substrate having an outer surface, a first cavity formed in the outer surface, a second cavity formed in the outer surface, and a dicing lane between the first and second cavities; a stack of first semiconductor dies in the first cavity; a stack of second semiconductor dies in the second cavity; a third semiconductor die attached to the outer surface of the semiconductor substrate and enclosing the stack of first semiconductor dies within the first cavity; and a fourth semiconductor die attached to the outer surface of the semiconductor substrate and enclosing the stack of second semiconductor dies within the second cavity.

2 . The semiconductor device assembly of claim 1 wherein the first cavity has at least one dimension different than a corresponding dimension of the second cavity.

3 . The semiconductor device assembly of claim 1 wherein the number of first semiconductor dies is greater than the number of second semiconductor dies.

4 . The semiconductor device assembly of claim 3 wherein at least one dimension of the first cavity is greater than a corresponding dimension of the second cavity.

5 . The semiconductor device assembly of claim 1 wherein
the first cavity is defined by a first recessed surface of the semiconductor substrate and a first sidewall surface of the semiconductor substrate extending from the first recessed surface, the first sidewall surface separated from the stack of first semiconductor dies by a first gap,
the second cavity is defined by a second recessed surface of the semiconductor substrate and a second sidewall surface of the semiconductor substrate extending from the second recessed surface, the second sidewall surface separated from the stack of second semiconductor dies by a second gap, and
the semiconductor device further comprises an underfill material having a first fillet in the first gap and a second fillet in the second gap.

6 . The semiconductor device assembly of claim 5 wherein a portion of a surface of the third semiconductor die is exposed in the first gap, and wherein a portion of a surface of the fourth semiconductor die is exposed in the second gap.

7 . The semiconductor device assembly of claim 1 wherein the semiconductor substrate, the first semiconductor dies, the second semiconductor dies, the third semiconductor die, and the fourth semiconductor die are each formed from the same semiconductor material.

8 . The semiconductor device assembly of claim 1 wherein the semiconductor material comprises silicon.

9 . The semiconductor device assembly of claim 1 wherein
the third semiconductor die has a base region attached to an uppermost one of the first semiconductor dies, and a peripheral region adjacent to the base region and attached to the outer surface of the semiconductor substrate, and
the fourth semiconductor die has a base region attached to an uppermost one of the second semiconductor dies, and a peripheral region adjacent to the base region and attached to the outer surface of the semiconductor substrate.

10 . A method of forming semiconductor device assemblies, comprising:
positioning a stack of first semiconductor dies in a first cavity of a semiconductor wafer formed from a semiconductor material; positioning a stack of second semiconductor dies in a second cavity of the semiconductor wafer; attaching a portion of a third semiconductor die to the semiconductor wafer such that the third semiconductor die covers an opening of the first cavity; attaching a portion of a fourth semiconductor die to the semiconductor wafer such that the fourth semiconductor die covers an opening of the second cavity; and singulating the semiconductor wafer along a dicing lane between the first and second cavities.

11 . The method of claim 10 , further comprising forming the first and second cavities in the semiconductor wafer.

12 . The method of claim 11 wherein at least one of a width, length, or shape of the first cavity is based on a shape of the stack of first semiconductor dies, and wherein at least one of a width, length, or shape of the second cavity is based on a shape of the stack of second semiconductor dies.

13 . The method of claim 12 wherein at least one of the width, length, or shape of the first cavity is different than the width, length, or shape of the second cavity.

14 . The method of claim 10 wherein
positioning the stack of first semiconductor dies in the first cavity includes positioning an initial one of the first semiconductor dies in the first cavity and subsequently stacking additional ones of the first semiconductor dies upon the initial one of the first semiconductor dies, and/or
positioning the stack of second semiconductor dies in the second cavity includes positioning an initial one of the second semiconductor dies in the second cavity and subsequently stacking additional ones of the second semiconductor dies upon the initial one of the second semiconductor dies.

15 . The method of claim 10 wherein
positioning the stack of first semiconductor dies in the first cavity includes mounting the first semiconductor dies in the first cavity collectively as a single unit, and/or
positioning the stack of second semiconductor dies in the second cavity includes mounting the second semiconductor dies in the second cavity collectively as a single unit.

16 . The method of claim 10 , further comprising thinning the semiconductor wafer at least below the first and second cavities.

17 . The method of claim 10 , further comprising flowing an underfill material between the first semiconductor dies and the second semiconductor dies.

18 . A semiconductor device assembly, comprising:
a semiconductor wafer formed from a semiconductor material, wherein the semiconductor wafer includes an inner region, an outer region projecting from the inner region, and a plurality of cavities defined in the outer region by the inner and outer regions; memory dies stacked in the cavities; logic dies including a base region and a peripheral region adjacent to the base region, wherein the base region of each logic die is attached to the semiconductor wafer, and wherein the logic dies enclose respective ones of the memory dies within the cavities; and wherein the semiconductor wafer further includes a plurality of dicing lanes between the logic dies.

19 . The semiconductor device assembly of claim 18 wherein the inner region of the semiconductor wafer below the cavities has a thickness of from about 50 μm to about 200 μm.

20 . The semiconductor device assembly of claim 18 , further comprising package support substrates electrically coupled to corresponding ones of the logic dies.

Assignees

• Micron Technology Inc

Inventors

• Vadhavkar Sameer S
• Gandhi Jaspreet S
• Derderian James M

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title