Division operations in memory

Patent metadata

Field	Value
Publication number	US-2017358333-A1
Application number	US-201715688348-A
Country	US
Kind code	A1
Filing date	Aug 28, 2017
Priority date	Sep 3, 2014
Publication date	Dec 14, 2017
Grant date	—

Abstract

Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. An example apparatus might include a second group of memory cells coupled to a second access line and configured to store a divisor element. An example apparatus might also include a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line.

First claim

1 - 13 . (canceled)

14 . A system comprising:
a first group of memory cells coupled to a first access line and configured to store a dividend element; a second group of memory cells coupled to a second access line and configured to store a divisor element; and a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations; wherein performing the number of operations comprises:
storing, as a first mask bit-vector, a bit pattern indicating at least one of a most significant bit (MSB) and a least significant bit (LSB) of at least one of a dividend bit-vector comprising the dividend element and a divisor bit-vector comprising the divisor element;
storing, as a second mask bit-vector, a bit pattern indicating at least one of the most significant bit (MSB) and the least significant bit (LSB) of multiple elements of at least one of the dividend bit-vector and the divisor bit-vector; and
performing a logical operation on the first mask bit-vector and a bit-vector stored in the sensing circuitry.

15 . The system of claim 14 , further comprising a memory device, including the first group of memory cells, the second group of memory cells, and the controller, coupled to a host.

16 . The system of claim 14 , wherein the host comprises a number of processors.

17 . The system of claim 14 , wherein the hosts provides an element width of the dividend bit-vector and the divisor bit-vector to the memory device and wherein the number of operations are performed in view of the element width.

18 . The system of claim 14 , wherein the number of operations comprises a number of AND operations, OR operations, and SHIFT operations.

19 . The system of claim 18 , wherein the sensing circuitry comprises a number of transistors formed on pitch with the memory cells and a sense amplifier and a compute component.

20 . The system of claim 19 , wherein the sense amplifier comprises a primary latch and the compute component comprises a secondary latch.

21 . A system comprising:
a memory array comprising:
a first group of memory cells coupled to a first access line and configured to store a plurality of dividend elements as a dividend bit-vector; and
a second group of memory cells coupled to a second access line and configured to store a plurality of divisor elements as a divisor bit-vector; and
a controller configured to control sensing circuitry to:
perform a plurality of division operations by dividing, in parallel, each one of the plurality of dividend elements by a respective one of the plurality of divisor elements;
store a plurality of results of the plurality of division operations in a third group of memory cells; and
wherein performing the plurality of division operations comprises:
storing, as a first mask bit-vector, a bit pattern indicating at least one of a most significant bit (MSB) and a least significant bit (LSB) of at least one of the dividend bit-vector and the divisor bit-vector;
storing, as a second mask bit-vector, a bit pattern indicating at least one of the most significant bit (MSB) and the least significant bit (LSB) of respective elements of at least one of the dividend bit-vector and the divisor bit-vector; and

performing a logical operation on the first mask bit-vector and a bit-vector stored in sensing circuitry coupled to the memory array.

22 . The system of claim 21 , wherein the memory array is located on a memory device coupled to a host.

23 . The system of claim 21 , wherein the plurality of results comprise a plurality of bit-vectors that represent at least one of a plurality of quotient elements and a plurality of remainder elements.

24 . The system of claim 21 , wherein the third group of memory cells is a same group of memory cells as at least one of:
the first group of memory cells coupled to the first access line; and the second group of memory cells coupled to the second access line.

25 . The system of claim 21 , wherein each of the plurality of division operations is performed on a different element pair including corresponding elements from the plurality of dividend elements and the plurality of divisor elements.

26 . A method of a system for performing division operations, comprising:
performing, in parallel, a plurality of division operations on:
a plurality (M) of dividend elements stored in a first group of memory cells coupled to a first access line and to a number (X) of sense lines of a memory array; and
a plurality (M) of divisor elements stored in a second group of memory cells coupled to a second access line and to the X of sense lines of the memory array; and
providing a plurality of quotient elements and a plurality of remainder elements; wherein performing the plurality of division operations comprises:
storing, as a mask bit-vector, a bit pattern indicating at least one of a most significant bit (MSB) and a least significant bit (LSB) of at least one of a dividend bit-vector comprising the plurality of dividend elements and a divisor bit-vector comprising the plurality of divisor elements; and
performing a logical operation on the mask bit-vector and a bit-vector stored in sensing circuitry coupled to the memory array.

27 . The method of claim 26 , wherein the plurality of dividend elements are a plurality of first values and the plurality of divisor elements are a plurality of second values.

28 . The method of claim 27 , wherein the plurality of first values are stored in the first group of memory cells as the dividend bit-vector and the plurality of second values are stored in the second group of memory cells as the divisor bit-vector.

29 . The method of claim 26 , wherein a number of operations used to perform the plurality of division operations in parallel is the same as a number of operations used to perform any one of the plurality of division operations.

30 . The method of claim 26 , wherein the mask bit-vector comprises at least one of a dynamic mask bit-vector and a static mask bit-vector and wherein performing the plurality of division operations includes performing a number (E) of iterations of operations.

31 . The method of claim 30 , wherein performing each of the E iterations of operations comprises:
storing the dynamic mask bit-vector, that identifies a MSB for each of the M dividend elements and the M divisor elements, in the sensing circuitry and in a group of memory cells that store a current dividend bit-vector; and performing a number (P) of iterations of operations, comprising:
shifting the current dividend bit-vector stored in the sensing circuitry;
inverting the shifted bit-vector in the sensing circuitry;
performing a first logical operation on the inverted bit-vector in the sensing circuitry and the static mask bit-vector that identify the MSB for each of the M dividend elements and the M divisor elements;
storing the result of the first logical operation in the sensing circuitry;
inverting the result of the first logical operation in the sensing circuitry; and
performing a second logical operation on the inverted result in the sensing circuitry and the current dividend bit-vector; and
storing the result of the second logical operation performed on the inverted result and the current dividend bit-vector in the group of memory cells that store the current dividend bit-vector.

32 . The method of claim 26 , wherein each of the M dividend elements and the M divisor elements are comprised of N bits.

Assignees

• Micron Technology Inc

Inventors

• Tiwari Sanjay

Classifications

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G06F12/0207

  with multidimensional access, e.g. row/column, matrix · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F12/02

  Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title