Pixel transfer rate boosting device

Patent metadata

Field	Value
Publication number	US-2017356798-A1
Application number	US-201715687772-A
Country	US
Kind code	A1
Filing date	Aug 28, 2017
Priority date	Dec 24, 2014
Publication date	Dec 14, 2017
Grant date	—

Abstract

A device, for pixel transfer rate boosting, is provided and includes an image sensing array having a plurality of pixel units, in which each of the plurality of pixel units is configured to generate a pixel signal when receiving an electromagnetic energy, a signal buffer circuit, electrically coupled with the image sensing array to receive the pixel signals, a switch circuit electrically coupled with the signal buffer circuit, a capacitor having a first terminal and a second terminal, in which the first terminal electrically couples with the switch circuit and the second terminal connects to a ground, a comparator, electrically coupled with the switch circuit, and a pull-down unit, electrically coupled with the first terminal of the capacitor and the switch circuit. After the switch circuit is turned on, the pull-down unit pulls the plurality of pixel output signals down.

First claim

What is claimed is:

1 . A device, comprising:
an image sensing array having a plurality of pixel units, wherein each of the plurality of pixel units is configured to generate a pixel signal when receiving an electromagnetic energy; a signal buffer circuit, electrically coupled with the image sensing array to receive the pixel signals; a switch circuit electrically coupled with the signal buffer circuit; a capacitor having a first terminal and a second terminal, in which the first terminal electrically couples with the switch circuit and the second terminal connects to a ground; a comparator, electrically coupled with the switch circuit; and a pull-down unit, electrically coupled with the first terminal of the capacitor and the switch circuit; wherein after the switch circuit is turned on, the signal buffer circuit generates a plurality of pixel output signals according to the pixel signals, and the pull-down unit is configured to pull the plurality of pixel output signals down.

2 . The device according to claim 1 , wherein the pull-down unit is an n-channel MOSFET (NMOS) having a gate, a source and a drain, and the drain being electrically coupled with the first terminal of the capacitor and the switch circuit.

3 . The device according to claim 1 , wherein the pull-down unit is an NMOS bank including a plurality of NMOSs and a plurality of switches, and each of the plurality of NMOSs having a gate, a source and a drain.

4 . The device according to claim 3 , wherein the drain of each of the plurality of NMOSs is electrically coupled with the first terminal of the capacitor and the switch circuit through each of the plurality of switches.

5 . The device according to claim 4 , wherein the NMOS bank further includes a control unit and the plurality of the switches are controlled by the control unit.

6 . The device according to claim 1 , wherein the signal buffer circuit is a unity gain buffer, or an NMOS source follower having a gate, a source and a drain.

7 . The device according to claim 1 , wherein the plurality of pixel output signals are substantially pulled down of 25% to 75%.

8 . The device according to claim 1 , wherein the plurality of pixel output signals are pulled down with a pull-down period ranging from 3 to 6 nanoseconds.

9 . The device according to claim 1 , wherein the plurality of pixel units are a complementary metal-oxide semiconductor (CMOS) or a charge-coupled device (CCD).

10 . A pull-down circuit, comprising:
a pixel unit, configured to generate a pixel signal when receiving an electromagnetic energy; a signal buffer circuit, electrically coupled with the pixel unit to receive the pixel signal and to output an output signal; a switch circuit electrically coupled with the signal buffer circuit; a capacitor having a first terminal and a second terminal, in which the first terminal electrically couples with the switch circuit and the second terminal connects to a ground; a comparator, electrically coupled with the switch circuit; and a pull-down unit, electrically coupled with the first terminal of the capacitor and the switch circuit; wherein after the switch circuit is turned on, and the signal buffer circuit generates a pixel output signal according to the pixel signal, and the pull-down unit is configured to pull the pixel output signal down.

11 . The pull-down circuit according to claim 10 , wherein the pull-down unit is an n-channel MOSFET (NMOS) having a gate, a source and a drain, and the drain being electrically coupled with the first terminal of the capacitor and the switch circuit.

12 . The pull-down circuit according to claim 10 , wherein the pull-down unit is a NMOS bank including a plurality of NMOSs and a plurality of switches, and each of the plurality of NMOSs having a gate, a source and a drain.

13 . The pull-down circuit according to claim 12 , wherein the drain of each of the plurality of NMOSs is electrically coupled with the first terminal of the capacitor and the switch circuit through each of the plurality of switches.

14 . The pull-down circuit according to claim 13 , wherein the NMOS bank further includes a control unit and the plurality of the switches are controlled by the control unit.

15 . The pull-down circuit according to claim 10 , wherein the signal buffer circuit is a unity gain buffer, or an NMOS source follower having a gate, a source and a drain.

16 . The pull-down circuit according to claim 10 wherein the pixel output signal is substantially pulled down of 25% to 75%.

17 . The pull-down circuit according to claim 10 , wherein the output signal is pulled down with a pull-down period ranging from 3 to 6 nanoseconds.

18 . The pull-down circuit according to claim 10 , wherein the pixel unit is a complementary metal-oxide semiconductor (CMOS) or a charge-coupled device (CCD).

Assignees

• Pixart Imaging Inc

Inventors

• Lim Wooi-Kip
• Liu Han-Chi

Classifications

• H04N25/59

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• G06F3/0383

  Signal control means within the pointing device · CPC title

• G01J1/46 Primary

  using a capacitor · CPC title

• G06F3/03543

  Mice or pucks (G06F3/03541 takes precedence) · CPC title