Controlling Temperature Of A System Memory

Patent metadata

Field	Value
Publication number	US-2017351308-A1
Application number	US-201715674594-A
Country	US
Kind code	A1
Filing date	Aug 11, 2017
Priority date	Aug 15, 2014
Publication date	Dec 7, 2017
Grant date	—

Abstract

In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . A processor comprising:
at least one core to execute instructions, the at least one core including:
an instruction fetcher to fetch instructions;
an instruction decoder to decode the instructions; and
one or more execution circuits to execute the decoded instructions; and
a memory controller coupled to the at least one core, the memory controller including a first circuit to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor in response to a temperature of the first memory device that exceeds a thermal threshold, the first memory device to be placed in an electrical idle state, wherein after the dynamic transfer the memory controller is to remap memory accesses from the first memory device to the second memory device.

2 . The processor of claim 1 , wherein the memory controller further comprises a plurality of first counters each associated with a memory device and to count a duration of a temperature of the associated memory device that exceeds the thermal threshold.

3 . The processor of claim 2 , wherein the first circuit is to cause the dynamic transfer further when a first counter of the plurality of first counters associated with the first memory device exceeds a second threshold.

4 . The processor of claim 2 , further comprising a second counter to count a number of times that the dynamic transfer has occurred between the first and second memory devices.

5 . The processor of claim 4 , wherein the first circuit, in response to the second counter exceeding a third threshold, is to disable the dynamic transfer and to cause the first memory device to be throttled.

6 . The processor of claim 5 , further comprising a configuration register to store the thermal threshold and the third threshold, wherein the configuration register is to be set by system software.

7 . The processor of claim 1 , wherein the thermal threshold comprises a throttle threshold, and the first circuit is to cause the dynamic transfer of the data and not a thermal throttle of the first memory device in response to the first memory device temperature that exceeds the thermal threshold.

8 . The processor of claim 1 , wherein the first memory device comprises a first dual inline memory module and the second memory device comprises a second dual inline memory module.

9 . The processor of claim 1 , wherein the first memory device comprises a first memory channel and the second memory device comprises a second memory channel.

10 . The processor of claim 1 , wherein the first circuit is to receive first temperature information of the first memory device from one or more thermal sensors of the first memory device.

11 . The processor of claim 1 , wherein the second memory device comprises a spare memory device, and the memory controller is to cause the second memory device to be in a low power state before the dynamic transfer.

12 . The processor of claim 1 , wherein the first circuit is to cause the dynamic transfer further in response to the temperature that exceeds the thermal threshold for a threshold duration.

13 . The processor of claim 12 , wherein the first circuit is to generate a system management interrupt in response to the temperature that exceeds the thermal threshold for the threshold duration.

14 . The processor of claim 1 , wherein the first circuit is to inform an operating system regarding the dynamic transfer.

15 . A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to execute a method comprising:
updating a first counter while a temperature of a first memory device coupled to a processor exceeds a thermal threshold; sending a signal to the first memory device to cause, during runtime of an application on the processor, an exchange of information between the first memory device and a second memory device coupled to the processor, in response to the first counter exceeding a first threshold; updating a second counter in response to the exchange; and in response to the second counter exceeding a second threshold, throttling one of the first memory device and the second memory device.

16 . The non-transitory machine-readable medium of claim 15 , wherein the method further comprises preventing further exchanges in response to the second counter exceeding the second threshold.

17 . The non-transitory machine-readable medium of claim 16 , wherein preventing the further exchanges comprises:
quiescing the information in the first memory device; setting the second memory device to an electrical idle state; and de-activating the second memory device.

18 . A system comprising:
a processor having at least one core to execute instructions and an integrated memory controller to interface with a volatile system memory, the memory controller including a dynamic hop circuit to enable data stored in a first portion of the volatile system memory to be dynamically transferred to a second portion of the volatile system memory when a temperature of the first portion of the volatile system memory exceeds a threshold temperature for longer than a threshold duration, wherein the second portion of the volatile system memory comprises a spare memory device; the volatile system memory including the first portion and the second portion; and a baseboard management controller coupled to the processor, wherein the integrated memory controller is to communicate thermal information regarding the volatile system memory to the baseboard management controller.

19 . The system of claim 18 , wherein the dynamic hop circuit is to be activated when the temperature of the first portion of the volatile system memory exceeds the threshold temperature for longer than the threshold duration, and otherwise to be in a low power state.

20 . The system of claim 18 , further comprising a plurality of fans, wherein the baseboard management controller is to control an operating speed of the plurality of fans.

Assignees

• Intel Corp

Inventors

• Rangarajan Thanunathan
• Risbud Vinayak P
• Yasmin Tabassum

Classifications

• G11C2029/0409

  Online test · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C29/76

  using address translation or modifications · CPC title

• G11C29/20

  using counters or linear-feedback shift registers [LFSR] · CPC title

• G06F2201/81

  Threshold · CPC title