Integrated Circuit Structure with Active and Passive Devices in Different Tiers

Patent metadata

Field	Value
Publication number	US-2017345791-A1
Application number	US-201715676427-A
Country	US
Kind code	A1
Filing date	Aug 14, 2017
Priority date	Sep 9, 2013
Publication date	Nov 30, 2017
Grant date	—

Abstract

An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure.

First claim

What is claimed is:

1 . A method comprising:
forming a first-tier chip comprising:
forming first active devices at a surface of a first semiconductor substrate; and
forming a first interconnect structure over the first semiconductor substrate, wherein the first-tier chip is free from passive devices therein;
bonding a second semiconductor substrate over the first interconnect structure; with the second semiconductor substrate being bonded on the first interconnect structure, forming second active devices at a surface of the second semiconductor substrate; forming a second interconnect structure over the second semiconductor substrate, wherein the second interconnect structure is electrically coupled to the second active devices and the first active devices; and forming a passive device in the second interconnect structure, wherein the second semiconductor substrate, the second interconnect structure, and the passive device in combination form a second-tier chip.

2 . The method of claim 1 further comprising, with the second semiconductor substrate being bonded on the first interconnect structure, thinning the second semiconductor substrate, wherein the second active devices are formed at the surface of the thinned second semiconductor substrate.

3 . The method of claim 1 , wherein the second semiconductor substrate is bonded to the first interconnect structure through silicon-to-oxide bonding.

4 . The method of claim 1 , wherein:
the first-tier chip comprises a first plurality of low-k dielectric layers, with upper ones of the first plurality of low-k dielectric layers being increasingly thicker than lower ones of the first plurality of low-k dielectric layers; and the second interconnect structure comprises a second plurality of low-k dielectric layers, with an upper one of the second plurality of low-k dielectric layers being thinner than a lower one of the second plurality of low-k dielectric layers.

5 . The method of claim 1 further comprising, after the second semiconductor substrate is thinned, forming a through-via penetrating through the second semiconductor substrate.

6 . The method of claim 1 , wherein the passive device in the second interconnect structure comprises is formed in a thickest dielectric layer in the second interconnect structure.

7 . The method of claim 6 further comprising forming a metal shielding pad covering the passive device.

8 . The method of claim 7 further comprising electrically grounding the metal shielding pad.

9 . A method comprising:
bonding a second semiconductor substrate to a first dielectric layer of a chip, wherein the chip comprises:
a first semiconductor substrate;
first active devices at a surface of the first semiconductor substrate;
a first interconnect structure over the first semiconductor substrate, wherein the first dielectric layer is at a top of the first interconnect structure;
thinning the second semiconductor substrate; forming second active devices at a surface of the thinned second semiconductor substrate; depositing a second dielectric layer over the second active devices; forming a plurality of through-vias penetrating through the second dielectric layer and the thinned second semiconductor substrate, wherein the plurality of through-vias is in contact with metal pads in the first dielectric layer; forming a second interconnect structure over the second semiconductor substrate; and forming a passive device in the second interconnect structure.

10 . The method of claim 9 , wherein the chip is free from passive devices therein.

11 . The method of claim 9 , wherein the thinning the second semiconductor substrate is performed when the second semiconductor substrate being bonded to the first dielectric layer of the chip.

12 . The method of claim 9 , wherein a thickest dielectric layer in the second interconnect structure is at an intermediate level of the second interconnect structure.

13 . The method of claim 12 , wherein the passive device comprises a portion in the thickest dielectric layer, and is selected from the group consisting essentially of an inductor, a transformer, and a transmission line.

14 . The method of claim 9 , wherein the forming the second interconnect structure further comprises:
forming a metal shielding pad overlapping the passive device; and electrically grounding a metal shielding pad.

15 . The method of claim 9 , wherein the forming the passive device comprises forming a capacitor over a plurality of low-k dielectric layer in the second interconnect structure, and the capacitor has a capacitor insulator being thinner than all dielectric layers in the second interconnect structure.

16 . A method comprising:
forming first active devices at a surface of a first semiconductor substrate; forming a first interconnect structure over the first semiconductor substrate, wherein the first interconnect structure comprises a first plurality of low-k dielectric layers, with upper ones of the first plurality of low-k dielectric layers being increasingly thicker than lower ones of the first plurality of low-k dielectric layers; bonding a second semiconductor substrate onto the first interconnect structure through silicon-to-oxide bonding or oxide-to-oxide bonding; thinning the second semiconductor substrate; forming second active devices on the second semiconductor substrate; and forming a second interconnect structure over the thinned second semiconductor substrate, wherein the second interconnect structure comprises a second plurality of low-k dielectric layers, with a first layer of the second plurality of low-k dielectric layers thicker than a second layer and a third layer of the second plurality of low-k dielectric layers, and the second layer is overlying the first layer, and the third layer is underlying the first layer.

17 . The method of claim 16 , wherein the second semiconductor substrate is free from active devices thereon when bonded to the first interconnect structure.

18 . The method of claim 16 further comprising:
forming a polymer layer over the second interconnect structure; and
forming a solder region on the polymer layer.

19 . The method of claim 16 further comprising forming through-vias penetrating through the second semiconductor substrate, wherein the through-vias land on metal pads in the first interconnect structure.

20 . The method of claim 16 , wherein no active device is formed at surfaces of the second semiconductor substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shih Yu-Nan

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title