APPARATUS AND METHOD FOR REDUCING di/dt

Patent metadata

Field	Value
Publication number	US-2017344090-A1
Application number	US-201615163494-A
Country	US
Kind code	A1
Filing date	May 24, 2016
Priority date	May 24, 2016
Publication date	Nov 30, 2017
Grant date	—

Abstract

Described is an apparatus which comprises: a controllable power gate coupled to an ungated power supply node and a gated power supply node; and a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node.

First claim

We claim:

1 . An apparatus comprising:
a controllable power gate coupled to an ungated power supply node and a gated power supply node; and a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node.

2 . The apparatus of claim 1 , wherein the charge-pump circuit is operable to turn on such that the gated power supply node is charged faster than when the charge-pump circuit is off.

3 . The apparatus of claim 1 , wherein the charge-pump circuit is operable to provide a constant current to the gated power supply node.

4 . The apparatus of claim 1 , wherein the charge-pump circuit is operable to turn off for at least two clock cycles.

5 . The apparatus of claim 1 , wherein the logic is to count edges of a clock and to generate a pulse to turn off the charge-pump circuit.

6 . The apparatus of claim 1 , wherein the charge-pump circuit comprises a multi-phase charge pump.

7 . The apparatus of claim 1 , wherein the controllable power gate comprises a primary power gate and a secondary power gate, wherein the primary power gate is larger than the secondary power gate.

8 . The apparatus of claim 7 , wherein the primary power gate comprises two or more transistors which are operable to turn on sequentially.

9 . The apparatus of claim 8 , wherein the secondary power gate comprises two or more transistors which are to turn on after at least one transistor of the primary power gate is turned on.

10 . The apparatus of claim 9 , wherein the transistors of the secondary power gate are configured in a daisy chain.

11 . An apparatus comprising:
an ungated power supply node; a gated power supply node; a primary power gate coupled to the ungated power supply node and the gated power supply node; a secondary power gate coupled to the ungated power supply node and the gated power supply node, the secondary power gate being smaller in size than the primary power gate; logic to generate a pulse; and a charge-pump circuit operable to be turned on and off according to the pulse, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node.

12 . The apparatus of claim 11 , wherein the charge-pump circuit is operable to provide a constant current to the gated power supply node.

13 . The apparatus of claim 11 , wherein the logic is to generate a first edge of the pulse after at least one clock cycle.

14 . The apparatus of claim 11 , wherein the charge pump circuit is to be turned off after the primary power gate is turned on.

15 . The apparatus of claim 11 , wherein the charge pump circuit is a multi-phase charge-pump circuit.

16 . A system comprising:
a memory; a processor coupled to the memory, the processor including:
a controllable power gate coupled to an ungated power supply node and a gated power supply node; and
a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node; and
a wireless interface for allowing the processor to communicate with another device.

17 . The system of claim 16 , wherein the charge-pump circuit is operable to turn on such that the gated power supply node is charged faster than when the charge-pump circuit is off.

18 . The system of claim 16 , wherein the charge-pump circuit is operable to provide a constant current to the gated power supply node.

19 . The system of claim 16 , wherein the charge-pump circuit is operable to turn off for at least two clock cycles.

20 . The system of claim 16 , wherein the logic is to count edges of a clock and to generate a pulse to turn off the charge-pump circuit.

Assignees

• Intel Corp

Inventors

• Kulkarni Jaydeep P
• Shim Yong
• Meinerzhagen Pascal A

Classifications

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• H02M1/0043

  Converters switched with a phase shift, i.e. interleaved (non-isolated DC/DC converters H02M3/1586) · CPC title