Efficient use of buffer space in a network switch

Patent metadata

Field	Value
Publication number	US-2017337010-A1
Application number	US-201615161316-A
Country	US
Kind code	A1
Filing date	May 23, 2016
Priority date	May 23, 2016
Publication date	Nov 23, 2017
Grant date	—

Abstract

Communication apparatus includes multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network. A memory is coupled to the ports and configured to contain both respective input buffers allocated to the ingress ports and a shared buffer holding data packets for transmission in multiple queues via the egress ports. Control logic is configured to monitor an overall occupancy level of the memory, and when a data packet is received through an ingress port having an input buffer that is fully occupied while the overall occupancy level of the memory is below a specified maximum, to allocate additional space in the memory to the input buffer and to accept the received data packet into the additional space.

First claim

1 . Communication apparatus, comprising:
multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network; a memory, coupled to the ports and configured to contain both respective input buffers allocated to the ingress ports and a shared buffer holding data packets for transmission in multiple queues via the egress ports; and control logic, which is configured to monitor an overall occupancy level of the memory, and when a data packet is received through an ingress port having an input buffer that is fully occupied while the overall occupancy level of the memory is below a specified maximum, to allocate additional space in the memory to the input buffer and to accept the received data packet into the additional space.

2 . The apparatus according to claim 1 , wherein the control logic is configured, when the overall occupancy level is above the specified maximum, to discard the received data packet.

3 . The apparatus according to claim 1 , wherein the control logic is configured to apply a predefined quota to the additional space that can be allocated to each input buffer, and to discard the received data packet when the quota has been filled.

4 . The apparatus according to claim 3 , wherein the control logic is configured, upon transmission of the data packet through a designated egress port or discard of the packet, to release the input buffer to receive further data packets.

5 . The apparatus according to claim 1 , wherein the control logic is configured to classify and queue the data packets received through the ingress ports into the multiple queues in the memory for transmission through the egress ports.

6 . The apparatus according to claim 5 , wherein the control logic is configured, responsively to respective classifications of the data packets, to transfer some of the data packets to the shared buffer while holding others of the data packets in the input buffers until the data packets are transmitted through the egress ports.

7 . The apparatus according to claim 6 , wherein the control logic is configured, upon transfer of the data packet from the input buffer to the shared buffer, to release the input buffer to receive further data packets only after verifying that a memory occupancy criterion is satisfied.

8 . The apparatus according to claim 1 , wherein the memory is configured so that the control logic can allocate any portion of the memory to the input buffers of the ingress ports.

9 . The apparatus according to claim 1 , wherein the control logic is configured to monitor the overall occupancy level of the memory by counting a first data volume of the data packets received through the ingress ports and a second data volume of the data packets transmitted through the egress ports.

10 . The apparatus according to claim 9 , wherein the control logic is configured to monitor respective fill levels of the input buffers by incrementing an input buffer count when a given data packet is written from the ingress port to a location in the memory, and decrementing the input buffer count when the given data packet is transferred to the egress ports or to the shared buffer and the additional space allocated in the memory to the input buffer is no longer occupied, and sufficient space is available in the memory to reduce the input buffer count.

11 . A method for communication, comprising:
receiving data packets from a packet data network through an ingress port of a network element having multiple ports configured to serve as ingress ports and egress ports; transferring the data packets from the ingress port to memory in the network element, which is configured to contain both respective input buffers allocated to the ingress ports and a shared buffer holding data packets for transmission in multiple queues via the egress ports; monitoring an overall occupancy level of the memory; and when a data packet is received through an ingress port having an input buffer that is fully occupied while the overall occupancy level of the memory is below a specified maximum, allocating additional space in the memory to the input buffer and accepting the received data packet into the additional space.

12 . The method according to claim 11 , and comprising, when the overall occupancy level is above the specified maximum, discarding the received data packet.

13 . The method according to claim 11 , wherein allocating the additional space comprises applying a predefined quota to the additional space that can be allocated to each input buffer, and discarding the received data packet when the quota has been filled.

14 . The method according to claim 13 , and comprising, upon transmission of the data packet through a designated egress port or discard of the packet, releasing the input buffer to receive further data packets.

15 . The method according to claim 11 , and comprising classifying and queuing the data packets received through the ingress ports into the multiple queues in the memory for transmission through the egress ports.

16 . The method according to claim 15 , wherein transferring the data packets comprises transferring some of the data packets, responsively to respective classifications of the data packets, to the shared buffer while holding others of the data packets in the input buffers until the data packets are transmitted through the egress ports.

17 . The method according to claim 16 , and comprising, upon transfer of the data packet from the input buffer to the shared buffer, releasing the input buffer to receive further data packets only after verifying that a memory occupancy criterion is satisfied.

18 . The method according to claim 11 , wherein the memory is configured so that any portion of the memory can be allocated to the input buffers of the ingress ports.

19 . The method according to claim 11 , wherein monitoring the overall occupancy level of the memory comprises counting a first data volume of the data packets received through the ingress ports and a second data volume of the data packets transmitted through the egress ports.

20 . The method according to claim 19 , and comprising monitoring respective fill levels of the input buffers by incrementing an input buffer count when a given data packet is written from the ingress port to a location in the memory, and decrementing the input buffer count when the given data packet is transferred to the egress ports or to the shared buffer and the additional space allocated in the memory to the input buffer is no longer occupied, and sufficient space is available in the memory to reduce the input buffer count.

Assignees

• Mellanox Tech Tlv Ltd

Inventors

• Kriss Roy
• Gafni Barak
• Elias George
• Rubinstein Eran
• Bar Tikva Shachar

Classifications

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0656 Primary

  Data buffering arrangements · CPC title

• H04L49/9036

  Common buffer combined with individual queues · CPC title

• H04L49/90

  Buffering arrangements · CPC title

• H04L49/103

  using a shared central buffer; using a shared memory · CPC title