Method for semiconductor device structure
US-12154970-B2 · Nov 26, 2024 · US
Semiconductor device and method for fabricating the same
US2017330954A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2017330954-A1 |
| Application number | US-201715667629-A |
| Country | US |
| Kind code | A1 |
| Filing date | Aug 3, 2017 |
| Priority date | Jun 9, 2014 |
| Publication date | Nov 16, 2017 |
| Grant date | — |
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Abstract
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A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.
First claim
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What is claimed is: 1 . A semiconductor device, comprising: an interfacial layer on a substrate; a gate structure on the interfacial layer, wherein the gate structure comprises a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different, wherein the horizontal direction width of the patterned high-k dielectric layer is taken in a horizontal direction from the substrate; a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer; and a second spacer on the sidewalls of the first spacer and the interfacial layer, wherein a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer. 2 . The semiconductor device of claim 1 , wherein the interfacial layer comprises silicon dioxide. 3 . The semiconductor device of claim 1 , wherein the gate structure comprises the patterned high-k dielectric layer, a patterned bottom barrier metal (BBM) layer on the patterned high-k dielectric layer, a patterned silicon layer on the patterned BBM layer, and a patterned hard mask on the patterned silicon layer. 4 . The semiconductor device of claim 3 , wherein the patterned BBM layer comprises TiN. 5 . The semiconductor device of claim 3 , wherein the patterned silicon layer comprises amorphous silicon or polysilicon. 6 . The semiconductor device of claim 1 , wherein the first spacer comprises silicon dioxide or silicon nitride. 7 . The semiconductor device of claim 1 , wherein the horizontal direction width of the interfacial layer is wider than a horizontal direction width of the gate structure. 8 . The semiconductor device of claim 1 , wherein an edge of the interfacial layer is aligned with an edge of the first spacer. 9 . The semiconductor device of claim 1 , further comprising a contact etch stop layer (CESL) around the second spacer, wherein a bottom surface of the CESL is lower than the planar bottom surface of the first spacer.
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Classifications
Electricity · mapped topic
Electricity · mapped topic
- H01L29/6656Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US2017330954A1 cover?
- A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are d…
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H01L29/6656. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Nov 16 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).