Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2017297901-A1
Application number	US-201715498009-A
Country	US
Kind code	A1
Filing date	Apr 26, 2017
Priority date	Feb 26, 2016
Publication date	Oct 19, 2017
Grant date	—

Abstract

A method of manufacturing a semiconductor structure includes receiving a first substrate including a dielectric layer disposed over the first substrate; forming a sensing structure and a bonding structure over the dielectric layer; disposing a conductive layer on the sensing structure; disposing a barrier layer over the dielectric layer; removing a first portion of the barrier layer to at least partially expose the conductive layer on the sensing structure; and removing a second portion of the barrier layer to at least partially expose the bonding structure.

First claim

1 . A method of manufacturing a semiconductor structure, comprising:
receiving a first substrate including a dielectric layer disposed over the first substrate; forming a sensing structure and a bonding structure over the dielectric layer; disposing a conductive layer on the sensing structure; disposing a barrier layer over the dielectric layer; removing a first portion of the barrier layer to at least partially expose the conductive layer on the sensing structure; and removing a second portion of the barrier layer to at least partially expose the bonding structure.

2 . The method of claim 1 , wherein the dielectric layer includes an oxide layer disposed over the first substrate and a nitride layer disposed over the oxide layer.

3 . The method of claim 1 , wherein the forming of the sensing structure and the bonding structure includes removing portions of the dielectric layer and disposing a conductive material within or over the dielectric layer.

4 . The method of claim 1 , further comprising disposing the conductive layer on the bonding structure.

5 . The method of claim 4 , wherein the disposing of the conductive layer on the sensing structure and the disposing of the conductive layer on the bonding structure are performed simultaneously.

6 . The method of claim 1 , wherein the disposing of the conductive layer includes sputtering or evaporation operations.

7 . The method of claim 1 , further comprising removing a portion of the conductive layer disposed over the bonding structure to at least partially expose the bonding structure.

8 . The method of claim 1 , wherein the removing of the first portion of the barrier layer is performed prior to the removing of the second portion of the barrier layer.

9 . The method of claim 1 , further comprising:
receiving a second semiconductor structure including a second substrate, a sacrificial oxide disposed over the second substrate, and a conductive plug disposed over the second substrate and extending through the sacrificial oxide; eutectically bonding the conductive plug with the bonding structure; and removing the sacrificial oxide.

10 . The method of claim 9 , wherein the conductive layer is at least partially exposed from the barrier layer upon the removing of the sacrificial oxide.

11 . The method of claim 9 , wherein the sacrificial oxide is removed by hydrofluoric acid (HF) vapor.

12 . A method of manufacturing a semiconductor structure, comprising:
receiving a substrate; disposing a first dielectric layer over the substrate; disposing a second dielectric layer over the first dielectric layer; forming a sensing structure and a bonding structure within or over the first dielectric layer and the second dielectric layer, disposing a first conductive layer on the sensing structure; disposing a second conductive layer on the bonding structure; disposing a barrier layer over the second dielectric layer and covering the first conductive layer and the second conductive layer; removing a first portion of the barrier layer to at least partially expose the first conductive layer; and removing a second portion of the barrier layer and a portion of the second conductive layer to at least partially expose the bonding structure.

13 . The method of claim 12 , wherein the bonding structure is partially exposed from the second conductive layer.

14 . The method of claim 12 , wherein the disposing of the first conductive layer is performed prior to the disposing of the second conductive layer.

15 . The method of claim 12 , wherein the barrier layer is resistant to hydrofluoric (HF) acid vapor.

16 . The method of claim 12 , wherein the removing of the first portion of the barrier layer includes forming a first recess over the first conductive layer.

17 . The method of claim 12 , wherein the removing of the second portion of the barrier layer includes forming a second recess over the bonding structure and surrounded by the second conductive layer.

18 . A method of manufacturing a semiconductor structure, comprising:
receiving a first substrate including a dielectric layer disposed over the first substrate; forming a sensing structure and a bonding structure over the dielectric layer; disposing a conductive layer on the sensing structure; disposing a barrier layer over the dielectric layer, the conductive layer and the bonding structure; and removing a portion of the barrier layer to at least partially expose the conductive layer and the bonding structure.

19 . The method of claim 18 , wherein the sensing structure is entirely covered by the conductive layer.

20 . The method of claim 18 , further comprising:
receiving a second substrate including a conductive plug protruded from the MEMS substrate; and bonding the conductive plug with the bonding structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Fu-Chun
• Yen Li-Chen
• Wu Tzu-Heng
• Tsai Yi-Heng
• Cheng Chun-Ren

Classifications

• B81B3/0086 Primary

  Electrical characteristics, e.g. reducing driving voltage, improving resistance to peak voltage · CPC title

• B81B2207/015

  the micromechanical device and the control or processing electronics being integrated on the same substrate · CPC title

• B81C1/00246

  Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate · CPC title

• B81B2207/07

  Interconnects · CPC title

• B81C2203/035

  Soldering · CPC title