Enhanced dynamic clock and voltage scaling (dcvs) scheme

Patent metadata

Field	Value
Publication number	US-2017293340-A1
Application number	US-201615094909-A
Country	US
Kind code	A1
Filing date	Apr 8, 2016
Priority date	Apr 8, 2016
Publication date	Oct 12, 2017
Grant date	—

Abstract

In certain aspects, a method for frequency scaling comprises determining whether only a subset of multiple processors is active, wherein the multiple processors share one or more resources. The method also comprises increasing a frequency of at least one processor in the subset of the multiple processors if a determination is made that only the subset of the multiple processors is active and the frequency of the at least one processor is below a frequency threshold. This may be done, for example, to increase the time duration of an idle mode for the one or more shared resources and achieve an overall power reduction for a system including the multiple processors, the one or more shared resources, and/or other function blocks.

First claim

What is claimed is:

1 . A method for frequency scaling, comprising:
determining whether only a subset of multiple processors is active, wherein the multiple processors share one or more resources; and increasing a frequency of at least one processor in the subset of the multiple processors if a determination is made that only the subset of the multiple processors is active and the frequency of the at least one processor is below a frequency threshold.

2 . The method of claim 1 , wherein the one or more resources comprise a memory and a memory controller, and the memory controller interfaces the multiple processors to the memory.

3 . The method of claim 2 , wherein the memory is external to a chip on which the multiple processors reside.

4 . The method of claim 1 , wherein increasing the frequency of the at least one processor comprises increasing the frequency of the at least one processor to the frequency threshold.

5 . The method of claim 1 , wherein the subset of the multiple processors includes one or more central processing units (CPUs), and one or more of the multiple processors outside the subset include at least one of a display processor, a video encoder/decoder, or a graphics processing unit (GPU).

6 . The method of claim 1 , further comprising:
determining a first frequency for the at least one processor based on a workload of the at least one processor; and setting the frequency of the at least one processor at the first frequency; wherein increasing the frequency of the at least one processor comprises increasing the frequency of the at least one processor from the first frequency to a second frequency if a determination is made that only the subset of the multiple processors is active and the first frequency is below a frequency threshold.

7 . The method of claim 6 , wherein the second frequency equals the frequency threshold.

8 . The method of claim 6 , further comprising decreasing the frequency of the at least one processor from the second frequency back to the first frequency if one or more of the multiple processors outside of the subset becomes active.

9 . An apparatus for frequency scaling, comprising:
means for determining whether only a subset of multiple processors is active, wherein the multiple processors share one or more resources; and means for increasing a frequency of at least one processor in the subset of the multiple processors if a determination is made that only the subset of the multiple processors is active and the frequency of the at least one processor is below a frequency threshold.

10 . The apparatus of claim 9 , wherein the one or more resources comprise a memory and a memory controller, and the memory controller interfaces the multiple processors to the memory.

11 . The apparatus of claim 10 , wherein the memory is external to a chip on which the multiple processors reside.

12 . The apparatus of claim 9 , wherein the means for increasing the frequency of the at least one processor comprises means for increasing the frequency of the at least one processor to the frequency threshold.

13 . The apparatus of claim 9 , wherein the subset of the multiple processors includes one or more central processing units (CPUs), and one or more of the multiple processors outside the subset include at least one of a display processor, a video encoder/decoder, or a graphics processing unit (GPU).

14 . The apparatus of claim 9 , further comprising:
means for determining a first frequency for the at least one processor based on a workload of the at least one processor; and means for setting the frequency of the at least one processor at the first frequency; wherein the means for increasing the frequency of the at least one processor comprises means for increasing the frequency of the at least one processor from the first frequency to a second frequency if a determination is made that only the subset of the multiple processors is active and the first frequency is below a frequency threshold.

15 . The apparatus of claim 14 , wherein the second frequency equals the frequency threshold.

16 . The apparatus of claim 14 , further comprising means for decreasing the frequency of the at least one processor from the second frequency back to the first frequency if one or more of the multiple processors outside of the subset becomes active.

17 . A system, comprising:
multiple processors, wherein the multiple processors share one or more resources; and a resource manager configured to determine whether only a subset of the multiple processors is active, and to increase a frequency of at least one processor in the subset of the multiple processors if a determination is made that only the subset of the multiple processors is active and the frequency of the at least one processor is below a frequency threshold.

18 . The system of claim 17 , wherein the one or more resources comprise a memory and a memory controller, and the memory controller interfaces the multiple processors to the memory.

19 . The system of claim 18 , wherein the memory is external to a chip on which the multiple processors reside.

20 . The system of claim 17 , wherein the resource manager is configured to increase the frequency of the at least one processor to the frequency threshold.

21 . The system of claim 17 , wherein the subset of the multiple processors includes one or more central processing units (CPUs), and one or more of the multiple processors outside the subset include at least one of a display processor, a video encoder/decoder, or a graphics processing unit (GPU).

22 . The system of claim 17 , wherein the resource manager is configured to determine a first frequency for the at least one processor based on a workload of the at least one processor, and set the frequency of the at least one processor at the first frequency, wherein the resource manager is configured to increase the frequency of the at least one processor from the first frequency to a second frequency if a determination is made that only the subset of the multiple processors is active and the first frequency is below a frequency threshold.

23 . The system of claim 22 , wherein the second frequency equals the frequency threshold.

24 . The system of claim 22 , wherein the resource manager is configured to decrease the frequency of the at least one processor from the second frequency back to the first frequency if one or more of the multiple processors outside of the subset becomes active.

Assignees

• Qualcomm Inc

Inventors

• Park Hee Jun
• Duroiu Cristian

Classifications

• G06F1/329

  by task scheduling · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/3265

  Power saving in display device · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title