Ultrasonic lamination of dielectric circuit materials

US2017290172A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017290172-A1
Application numberUS-201615331307-A
CountryUS
Kind codeA1
Filing dateOct 21, 2016
Priority dateApr 4, 2016
Publication dateOct 5, 2017
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of lamination of dielectric circuit materials is provided. The method includes preparing first and second circuit layers of dielectric materials, stacking the first and second circuit layers with circuit trace elements interposed between the first and second circuit layers and ultrasonically welding the second circuit layer onto the first circuit layer around the circuit trace elements.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of lamination of dielectric circuit materials, the method comprising: preparing first and second circuit layers of dielectric materials; stacking the first and second circuit layers with circuit trace elements interposed between the first and second circuit layers; and ultrasonically welding the second circuit layer onto the first circuit layer around the circuit trace elements. 2 . The method according to claim 1 , wherein the dielectric materials comprise liquid crystal polymer (LCP), Polyimides and Polytetrafluoroethylene (PTFE). 3 . The method according to claim 1 , wherein the ultrasonically welding comprises melting material of the second circuit layer without melting material of the first circuit layer. 4 . The method according to claim 1 , further comprising: machining a cavity in the first circuit layer; stacking the first and second circuit layers such that the second circuit layer overhangs the cavity; and avoiding an execution of ultrasonic welding at a location of the cavity. 5 . The method according to claim 4 , further comprising disposing an electrical or thermal element into the cavity. 6 . The method according to claim 1 , further comprising installing vias by which circuit trace elements are connectable. 7 . The method according to claim 1 , wherein an execution of ultrasonic welding bonds abutting circuit trace elements. 8 . The method according to claim 1 , further comprising machining, re-melting or polishing the second circuit layer to have a predetermined thickness or surface roughness. 9 . A method of lamination of dielectric circuit materials, the method comprising: preparing first and second circuit layers of dielectric materials; disposing circuit trace elements on at least one of an upper surface of the first circuit layer and a lower surface of the second circuit layer; stacking the first and second circuit layers such that the lower surface of the second circuit layer above the upper surface of the first circuit layer; and ultrasonically welding the lower surface of the second circuit layer onto the upper surface of the first circuit layer around the circuit trace elements. 10 . The method according to claim 9 , wherein the dielectric materials comprise liquid crystal polymer (LCP), Polyimides and Polytetrafluoroethylene (PTFE). 11 . The method according to claim 9 , wherein the ultrasonically welding comprises melting material of the lower surface of the second circuit layer without melting material of the upper surface of the first circuit layer. 12 . The method according to claim 9 , further comprising localizing an execution of ultrasonic welding. 13 . The method according to claim 9 , further comprising controlling a single horn element to conduct the stacking and the ultrasonically welding. 14 . The method according to claim 9 , further comprising: machining a cavity in the upper surface of the first circuit layer; stacking the first and second circuit layers such that the second circuit layer overhangs the cavity; and avoiding an execution of ultrasonic welding at a location of the cavity. 15 . The method according to claim 14 , further comprising disposing an electrical or thermal element into the cavity. 16 . The method according to claim 9 , further comprising installing vias by which circuit trace elements are connectable. 17 . The method according to claim 9 , wherein an execution of ultrasonic welding bonds abutting circuit trace elements. 18 . The method according to claim 9 , further comprising machining, re-melting or polishing the second circuit layer to have a predetermined thickness or surface roughness. 19 . A method of lamination of dielectric circuit materials, the method comprising: preparing a first circuit layer of first dielectric materials and a second circuit layer of second dielectric materials; stacking the first and second circuit layers with circuit trace elements interposed between the first and second circuit layers; ultrasonically welding the second dielectric material onto the first dielectric material around the circuit trace elements; bonding circuit trace elements abutting other circuit trace elements; and bonding the first or second dielectric materials to circuit trace elements to which the first or second dielectric materials abut. 20 . The method according to claim 19 , wherein the bonding is achieved by at least one of ultrasonic welding, soldering and adhesion.

Assignees

Inventors

Classifications

  • Binding insulating layers without adhesive, e.g. by local heating or welding, before lamination of the whole PCB · CPC title

  • Fluoropolymer, e.g. polytetrafluoroethylene [PTFE] · CPC title

  • Using ultrasound, e.g. for cleaning, soldering or wet treatment · CPC title

  • Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence) · CPC title

  • Liquid crystal polymer [LCP] · CPC title

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What does patent US2017290172A1 cover?
A method of lamination of dielectric circuit materials is provided. The method includes preparing first and second circuit layers of dielectric materials, stacking the first and second circuit layers with circuit trace elements interposed between the first and second circuit layers and ultrasonically welding the second circuit layer onto the first circuit layer around the circuit trace elements.
Who is the assignee on this patent?
Raytheon Co
What technology area does this patent fall under?
Primary CPC classification H05K3/4632. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Oct 05 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).