Graded buffer layers with lattice matched epitaxial oxide interlayers

Patent metadata

Field	Value
Publication number	US-2017288024-A1
Application number	US-201615085022-A
Country	US
Kind code	A1
Filing date	Mar 30, 2016
Priority date	Mar 30, 2016
Publication date	Oct 5, 2017
Grant date	—

Abstract

A lattice matched epitaxial oxide interlayer is disposed between each semiconductor layer of a graded buffer layer material stack. Each lattice matched epitaxial oxide interlayer inhibits propagation of threading dislocations from one semiconductor layer of the graded buffer layer material stack into an overlying semiconductor layer of the graded buffer layer material stack. This allows for decreasing the thickness of each semiconductor layer within the graded buffer layer material stack. The topmost semiconductor layer of the graded buffer layer material stack, which is a relaxed layer, contains a lower defect density than the other semiconductor layers of the graded buffer layer material stack.

First claim

1 . A semiconductor structure comprising:
a graded buffer layer material stack located on a surface of a semiconductor substrate, wherein a lattice matched epitaxial oxide interlayer is disposed between each semiconductor layer of said graded buffer layer material stack and wherein a bottommost semiconductor layer of said graded buffer layer material stack is located directly on said surface of said semiconductor substrate and wherein each semiconductor layer of said graded buffer layer material stack is relaxed and a topmost semiconductor layer of said graded buffer layer material stack contains a lower defect density than other semiconductor layers of said graded buffer layer stack, and wherein threading dislocation defects are present in each semiconductor layer of said graded buffer layer material stack beneath said topmost semiconductor layer, and said threading dislocation defects that are present in each semiconductor layer of said graded buffer layer material stack beneath said topmost semiconductor layer terminate at a bottommost surface of one of said lattice matched oxide interlayers.

2 . The semiconductor structure of claim 1 , wherein each semiconductor layer of said graded buffer layer material stack is composed of a silicon germanium alloy.

3 . The semiconductor structure of claim 2 , wherein said graded buffer layer material stack containing said silicon germanium alloy is step graded.

4 . The semiconductor structure of claim 1 , wherein each semiconductor layer of said graded buffer layer material stack is composed of a III-V compound semiconductor material.

5 . The semiconductor structure of claim 4 , wherein said graded buffer layer material stack containing said III-V compound semiconductor material is step graded.

6 . The semiconductor structure of claim 1 , wherein each of said lattice matched epitaxial oxide interlayers is composed of an oxide of at least one rare earth metal.

7 . The semiconductor structure of claim 6 , wherein said oxide of said at least one rare earth metal is (La x Y 1-x ) 2 O 3 wherein x is from 0.33 to 0.46.

8 . The semiconductor structure of claim 6 , wherein said oxide of said at least one rare earth metal is selected from the group consisting of Gd 2 O 3 , Er 2 O 3 , Dy 2 O 3 , Ho 2 O 3 , Tm 2 O 3 , Lu 2 O 3 and CeO 2 .

9 . (canceled)

10 . The semiconductor structure of claim 1 , wherein misfit dislocation defects are present within a bottom portion of each semiconductor layer of said graded buffer layer material stack.

11 . (canceled)

12 . A method of forming a semiconductor structure, said method comprising:
forming a graded buffer layer material stack on a surface of a semiconductor substrate, wherein a lattice matched epitaxial oxide interlayer is disposed between each semiconductor layer of said graded buffer layer material stack, and wherein a bottommost semiconductor layer of said graded buffer layer material stack is located directly on said surface of said semiconductor substrate and wherein each semiconductor layer of said graded buffer layer material stack is relaxed and a topmost semiconductor layer of said graded buffer layer material stack contains a lower defect density than other semiconductor layers of said graded buffer layer stack, and wherein threading dislocation defects are present in each semiconductor layer of said graded buffer layer material stack beneath said topmost semiconductor layer, and said threading dislocation defects that are present in each semiconductor layer of said graded buffer layer material stack beneath said topmost semiconductor layer terminate at a bottommost surface of one of said lattice matched oxide interlayers.

13 . The method of claim 12 , wherein each semiconductor layer of said graded buffer layer material stack is composed of a silicon germanium alloy.

14 . The method of claim 13 , wherein said graded buffer layer material stack containing said silicon germanium alloy is step graded.

15 . The method of claim 12 , wherein each semiconductor layer of said graded buffer layer material stack is composed of a III-V compound semiconductor material, and said graded buffer layer material stack containing said III-V compound semiconductor material is step graded.

16 . The method of claim 12 , wherein each of said lattice matched epitaxial oxide interlayers is composed of an oxide of at least one rare earth metal.

17 . The method of claim 16 , wherein said oxide of said at least one rare earth metal is (La x Y 1-x ) 2 O 3 wherein x is from 0.33 to 0.46.

18 . The method of claim 16 , wherein said oxide of said at least one rare earth metal is selected from the group consisting of Gd 2 O 3 , Er 2 O 3 , Dy 2 O 3 , Ho 2 O 3 , Tm 2 O 3 , Lu 2 O 3 and CeO 2 .

19 . The method of claim 12 , wherein said forming said graded buffer layer material containing said lattice matched oxide interlayers comprises:
epitaxially growing each semiconductor layer and epitaxially growing each lattice matched epitaxial oxide interlayer.

20 . The method of claim 12 , wherein misfit dislocation defects are present within a bottom portion of each semiconductor layer of said graded buffer layer material stack.

Assignees

• IBM

Inventors

• Reznicek Alexander

Classifications

• H10P14/3414

  being group IIIA-VIA materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3426

  Oxides · CPC title

• H10P14/3254

  Graded layers · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title