Synchronization processing unit, device, and system

Patent metadata

Field	Value
Publication number	US-2017286331-A1
Application number	US-201715472744-A
Country	US
Kind code	A1
Filing date	Mar 29, 2017
Priority date	Mar 31, 2016
Publication date	Oct 5, 2017
Grant date	—

Abstract

Disclosed are a synchronization processing unit etc. including a command determination unit that determines whether the memory access command is a command for synchronization processing; a completion determination unit that determines whether a memory access command is complete; an issuance unit configured to issue a memory access command determined not to be for the synchronization processing to the memory, and that suspends issuance of a memory access command determined to be for the synchronization processing until completion of a preceding memory access command received before the memory access command for the synchronization processing is determined and then issues the suspended memory access command; and a subsequent control unit that, during a period from the suspension of the memory access command to the issuance and then completion thereof, performs control so that a subsequent memory access command is not received from the external device and the processor in the device.

First claim

What is claimed is:

1 . A synchronization processing unit comprising:
a command determination unit configured to, upon receipt of a memory access command for accessing memory in a device including the synchronization processing unit from an external device connected to the device by an extension bus or from a processor in the device, determine whether or not the memory access command is a command for synchronization processing for instructing synchronization processing; a completion determination unit configured to determine whether a memory access command issued to the memory is complete or not; an issuance unit configured to issue a memory access command determined not to be for the synchronization processing to the memory, and that suspends issuance of a memory access command determined to be for the synchronization processing until completion of a preceding memory access command received before the memory access command for the synchronization processing is determined by the completion determination unit and then issues the suspended memory access command; and a subsequent control unit configured to, during a period from the suspension of the memory access command for the synchronization processing to the issuance and then completion thereof, perform control so that a subsequent memory access command is not received from the external device and the processor in the device.

2 . The synchronization processing unit according to claim 1 , wherein the command determination unit stores information that represents an area for the synchronization processing in the memory, and, based on whether or not an area in the memory that is a target of the received memory access command is included in the area for the synchronization processing, determines whether or not the memory access command is a command for the synchronization processing.

3 . The synchronization processing unit according to claim 1 , wherein the completion determination unit includes a counter that is incremented when the memory access command is issued to the memory and that is decremented when completion of the memory access command is notified, and, based on a value of the counter, determines whether the memory access command issued to the memory is complete or not.

4 . The synchronization processing unit according to claim 2 , wherein the completion determination unit includes a counter that is incremented when the memory access command is issued to the memory and that is decremented when completion of the memory access command is notified, and, based on a value of the counter, determines whether the memory access command issued to the memory is complete or not.

5 . A device comprising:
a synchronization processing unit including:
a command determination unit configured to, upon receipt of a memory access command for accessing memory in a device including the synchronization processing unit from an external device connected to the device by an extension bus or from a processor in the device, determine whether or not the memory access command is a command for synchronization processing for instructing synchronization processing;
a completion determination unit configured to determine whether a memory access command issued to the memory is complete or not;
an issuance unit configured to issue a memory access command determined not to be for the synchronization processing to the memory, and that suspends issuance of a memory access command determined to be for the synchronization processing until completion of a preceding memory access command received before the memory access command for the synchronization processing is determined by the completion determination unit and then issues the suspended memory access command; and
a subsequent control unit configured to, during a period from the suspension of the memory access command for the synchronization processing to the issuance and then completion thereof, perform control so that a subsequent memory access command is not received from the external device and the processor in the device; and
the memory; and
the processor.

6 . The device according to claim 5 , wherein
the command determination unit stores information that represents an area for the synchronization processing in the memory, and, based on whether or not an area in the memory that is a target of the received memory access command is included in the area for the synchronization processing, determines whether or not the memory access command is a command for the synchronization processing.

7 . The device according to claim 5 , wherein the completion determination unit includes a counter that is incremented when the memory access command is issued to the memory and that is decremented when completion of the memory access command is notified, and, based on a value of the counter, determines whether the memory access command issued to the memory is complete or not.

8 . The device according to claim 6 , wherein the completion determination unit includes a counter that is incremented when the memory access command is issued to the memory and that is decremented when completion of the memory access command is notified, and, based on a value of the counter, determines whether the memory access command issued to the memory is complete or not.

9 . A system comprising:
a device including:
a synchronization processing unit including:
a command determination unit configured to, upon receipt of a memory access command for accessing memory in a device including the synchronization processing unit from an external device connected to the device by an extension bus or from a processor in the device, determine whether or not the memory access command is a command for synchronization processing for instructing synchronization processing;
a completion determination unit configured to determine whether a memory access command issued to the memory is complete or not;
an issuance unit configured to issue a memory access command determined not to be for the synchronization processing to the memory, and that suspends issuance of a memory access command determined to be for the synchronization processing until completion of a preceding memory access command received before the memory access command for the synchronization processing is determined by the completion determination unit and then issues the suspended memory access command; and
a subsequent control unit configured to, during a period from the suspension of the memory access command for the synchronization processing to the issuance and then completion thereof, perform control so that a subsequent memory access command is not received from the external device and the processor in the device;

the memory; and
the processor; and
a host device as the external device.

10 . The system according to claim 9 , wherein
the command determination unit stores information that represents an area for the synchronization processing in the memory, and, based on whether or not an area in the memory that is a target of the received memory access command is included in the area for the synchronization processing, determines whether or not the memory access command is a command for the synchronization processing.

11 . The system according to claim 9 , wherein the completion determination unit includes a counter that is incremented when the memory access command is issued to the memory and that is decremented when completion of the memory access command is notified, and, based on a value of the counter, determines whether the memory access command issued to the memory is complete or not.

12 . The system according to claim 10 , wherein the completion de

Assignees

• Nec Corp

Inventors

• Kobayashi Yuusuke
• Yamada Yohei

Classifications

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F13/4068

  Electrical coupling · CPC title