Memory system and operating method of memory system

US2017277476A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017277476-A1
Application numberUS-201615266128-A
CountryUS
Kind codeA1
Filing dateSep 15, 2016
Priority dateMar 25, 2016
Publication dateSep 28, 2017
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A memory system may include: a memory device comprising a plurality of pages, which include a plurality of memory cells coupled to a plurality of word lines, and in which data is stored, and a plurality of memory blocks in which the pages are included; and a controller configured to divide the memory blocks into a first group and a second group, perform a command operation corresponding to a command received from a host, and respectively store segments of user data and meta data for the command operation in memory blocks included in the first group or memory blocks included in the second group, in accordance with type information of the user data Included in the command.

First claim

Opening claim text (preview).

What is claimed is: 1 . A memory system comprising: a memory device including a plurality of memory blocks; and a controller suitable for dividing the memory blocks into a first group and a second group, performing a command operation corresponding to a command received from a host, and respectively storing segments of user data and meta data for the command operation in memory blocks included in the first group or memory blocks included in the second group, in accordance with at least one information included in the meta data information of the user data. 2 . The memory system according to claim 1 , wherein the controller classifies the segments into a first type and a second type in accordance with type information included in the meta data information of the user data, and the controller stores segments of the first type in the memory blocks of the first group, and stores segments of the second type in the memory blocks of the second group. 3 . The memory system according to claim 2 , wherein the segments of the first type are segments of the user data and meta data for which, after being stored in the memory blocks of the first group, only a read operation of the command operation is performed. 4 . The memory system according to claim 3 , wherein the controller checks a read count in accordance with the read operation for the segments of the first type, and the controller classifies the segments of the first type into a third type and a fourth type in accordance with the read count. 5 . The memory system according to claim 4 , wherein the controller migrates and stores segments of the third type stored in the memory blocks of the first group, to a first memory block of the first group, and the controller migrates and stores segments of the fourth type stored in the memory blocks of the first group, to a second memory block of the first group. 6 . The memory system according to claim 5 , wherein the first memory block includes a Multi Level Cell (MLC) memory block, and the second memory block includes a Triple Level Cell (TLC) memory block. 7 . The memory system according to claim 4 , wherein the segments of the third type are segments of hot data, and the segments of the fourth type are segments of cold data. 8 . The memory system according to claim 2 , wherein the segments of the second type are segments of the user data and meta data for which, after being stored in the memory blocks of the first group, an update operation of the command operation is performed. 9 . The memory system according to claim wherein the controller stores the segments of the second type in first memory blocks, among the memory blocks of the second group, and then migrates and stores the segments of the second type to second memory blocks. 10 . The memory system according to claim 9 , wherein the first memory blocks include Single Level Cell (SLC) memory blocks and Multi Level Cell (MLC) memory blocks, and wherein the second memory blocks include the MLC memory blocks and Triple Level Cell (TLC) memory blocks. 11 . An operating method of a memo system comprising: receiving a command from a host; checking user data included in the command and type information of the user data; dividing a plurality of memory blocks of a memory device into a first group and a second group; and performing a command operation corresponding to the command, and storing segments of the user data and meta data for the command operation in memory blocks included in the first group or memory blocks included in the second group, in accordance with the type information. 12 . The operating method of claim 11 , wherein the storing comprises: classifying the segments into a first type and a second type in accordance with the type information; and storing segments of the first type in the memory blocks of the first group, and storing segments of the second type in the memory blocks of the second group. 13 . The operating method according to claim 12 , wherein the segments of the first type are segments of the user data and meta data for which, after being stored in the memory blocks of the first group, only a read operation of the command operation is performed. 14 . The operating method according to claim 13 , further comprising: checking a read count in accordance with the read operation for the segments of the first type; and classifying the segments of the first type into a third type and a fourth type in accordance with the read count. 15 . The operating method according to claim 14 , further comprising: migrating and storing segments of the third type stored in the memory blocks of the first group, to a first memory block of the first group; and migrating and storing segments of the fourth type stored in the memory blocks of the first group, to a second memory block of the first group. 16 . The operating method according to claim 15 , wherein the first memory block includes a Multi Level Cell (MLC) memory block, and wherein the second memory block includes a Triple Level Cell (TLC) memory block. 17 . The operating method according to claim 14 , wherein the segments of the third type are segments of hot data, and wherein the segments of the fourth type are segments of cold data. 18 . The operating method according to claim 12 , wherein the segments of the second type are segments of the user data and meta data for which, after being stored in the memory blocks of the first group, an update operation of the command operation is performed. 19 . The memory system according to claim 18 , wherein the storing comprises migrating and storing the segments of the second type in first memory blocks, among the memory blocks of the second group, and then migrating and storing the segments of the second type to second memory blocks. 20 . The operating method according to claim 19 , wherein the first memory blocks include Single Level Cell (SLC) memory blocks and Multi Level Cell (MLC) memory blocks, and the second memory blocks include the MLC memory blocks and Triple Level Cell (TLC) memory blocks.

Assignees

Inventors

Classifications

  • Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

  • Improving or facilitating administration, e.g. storage management · CPC title

  • G06F3/0673Primary

    Single storage device · CPC title

  • Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

  • Non-volatile semiconductor memory arrays · CPC title

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Frequently asked questions

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What does patent US2017277476A1 cover?
A memory system may include: a memory device comprising a plurality of pages, which include a plurality of memory cells coupled to a plurality of word lines, and in which data is stored, and a plurality of memory blocks in which the pages are included; and a controller configured to divide the memory blocks into a first group and a second group, perform a command operation corresponding to a co…
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification G06F3/0673. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Sep 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).