Semiconductor memory device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2017271584-A1
Application number	US-201615387207-A
Country	US
Kind code	A1
Filing date	Dec 21, 2016
Priority date	Mar 18, 2016
Publication date	Sep 21, 2017
Grant date	—

Abstract

According to one embodiment, a semiconductor memory device includes a semiconductor layer, a gate electrode, a metal containing portion, and an insulating portion. The semiconductor layer includes a first region and a second region. The second region has at least one of a region being amorphous or a region having a crystallinity lower than a crystallinity of the first region. The gate electrode is apart from the first region in a first direction. The first direction crosses a second direction connecting the first region and the second region. The metal containing portion is apart from the second region in the first direction. At least a part of the metal containing portion overlaps the gate electrode in the second direction. The insulating portion is provided between the gate electrode and the first region and between the metal containing portion and the second region.

First claim

What is claimed is:

1 . A semiconductor memory device, comprising:
a semiconductor layer including a first region and a second region, the second region including at least one of a region being amorphous or a region having a crystallinity lower than a crystallinity of the first region; a gate electrode apart from the first region in a first direction, the first direction crossing a second direction connecting the first region and the second region; a metal containing portion apart from the second region in the first direction, at least a part of the metal containing portion overlapping the gate electrode in the second direction; and an insulating portion provided between the gate electrode and the first region and between the metal containing portion and the second region.

2 . The device according to claim 1 , wherein the metal containing portion includes at least one selected from the group consisting of silver, copper, nickel, cobalt, aluminum, titanium, tantalum, and tungsten.

3 . The device according to claim 1 , further comprising a controller,
the semiconductor layer further including a third region, at least a part of the first region being disposed between the second region and the third region, the controller being electrically connected with the gate electrode, the metal containing portion, and the third region, the controller being configured to perform:
a first operation of applying a first voltage to the third region, applying a second voltage to the gate electrode, and applying a third voltage to the metal containing portion, the second voltage being higher than the first voltage, the third voltage being higher than the first voltage; and
a second operation of applying a fourth voltage to the third region, applying a fifth voltage to the gate electrode, and applying a sixth voltage to the metal containing portion, the fifth voltage being higher than the fourth voltage, the sixth voltage being lower than the fourth voltage,
a first electrical resistance between the third region and the metal containing portion in a first state being different from a second electrical resistance between the third region and the metal containing portion in a second state, the first state being after the first operation and having a seventh voltage applied to the third region and an eighth voltage applied to the gate electrode, the eighth voltage being higher than the seventh voltage, the second state being after the second operation and having the seventh voltage applied to the third region and the eighth voltage applied to the gate electrode.

4 . The device according to claim 1 , wherein
the semiconductor layer includes a first conductive region and a second conductive region, the first region is positioned between the first conductive region and the second conductive region, and the second region is positioned inside the first conductive region.

5 . The device according to claim 3 , wherein
the semiconductor layer includes a first conductive region and a second conductive region, the first region is positioned between the first conductive region and the second conductive region, the second region is positioned inside the first conductive region, and the third region is positioned inside the second conductive region.

6 . The device according to claim 1 , wherein the metal containing portion includes a chalcogenide compound including at least one selected from the group consisting of silver, copper, nickel, cobalt, aluminum, titanium, tantalum, and tungsten.

7 . The device according to claim 1 , wherein
the semiconductor layer includes silicon, and a concentration of argon in the second region is higher than a concentration of argon in the first region.

8 . The device according to claim 1 , wherein
the semiconductor layer includes silicon, and a concentration of phosphorus in the second region is higher than a concentration of phosphorus in the first region.

9 . The device according to claim 1 , wherein
the semiconductor layer includes silicon, and a concentration of germanium in the second region is higher than a concentration of germanium in the first region.

10 . The device according to claim 1 , wherein a length of the metal containing portion along the first direction is not less than 1 nanometer and less than 100 nanometers.

11 . The device according to claim 1 , wherein a length of the insulating portion along the first direction between the metal containing portion and the second region is not less than 2 nanometers and less than 100 nanometers.

12 . The device according to claim 1 , wherein
the metal containing portion includes a first portion and a second portion, the second portion is located between the first portion and the second region, and a length of the first portion along the second direction is longer than a length of the second portion along the second direction.

13 . The device according to claim 1 , wherein
the metal containing portion is provided in a plurality, and the plurality of the metal containing portions are arranged along the second direction.

14 . A semiconductor memory device, comprising:
a semiconductor layer including silicon, the semiconductor layer including a first region and a second region, the second region including a first element including at least one selected from the group consisting of argon, phosphorus, and germanium, a concentration of the first element in the second region being higher than a concentration of the first element in the first region; a gate electrode apart from the first region in a first direction, the first direction crossing a second direction connecting the first region and the second region; a metal containing portion apart from the second region in the first direction, at least a part of the metal containing portion overlapping the gate electrode in the second direction, the metal containing portion including a first portion and a second portion, the second portion being located between the first portion and the second region, a length of the first portion along the second direction being longer than a length of the second portion along the second direction; and an insulating portion provided between the gate electrode and the first region and between the metal containing portion and the second region.

15 . The device according to claim 14 , wherein the metal containing portion includes at least one selected from the group consisting of silver, copper, nickel, cobalt, aluminum, titanium, tantalum, and tungsten.

16 . A method for manufacturing a semiconductor memory device, comprising:
forming a gate electrode on a first region of a semiconductor layer; implanting ions into a second region of the semiconductor layer to perform at least one of amorphizing the second region or causing a crystallinity of the second region to be lower than a crystallinity of the first region; and forming, after the implanting, a metal containing portion on the second region with an insulating portion interposed.

Assignees

• Toshiba Kk

Inventors

• Yamaguchi Marina
• Fujii Shosuke
• Saitoh Masumi
• Kuriyama Hiromichi
• Konno Takuya

Classifications

• H01L45/085

  Electricity · mapped topic

• H01L45/1206 Primary

  Electricity · mapped topic

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title

• H01L27/2436

  Electricity · mapped topic

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title