Semiconductor device and method for manufacturing same

US2017263633A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017263633-A1
Application numberUS-201615262274-A
CountryUS
Kind codeA1
Filing dateSep 12, 2016
Priority dateMar 11, 2016
Publication dateSep 14, 2017
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

According to the embodiment, a semiconductor device includes: a substrate; a stacked body provided on the substrate and including a plurality of electrode layers stacked with an insulator interposed; a semiconductor pillar provided on the substrate and in the stacked body; a semiconductor body provided in the stacked body; and an insulating film including a charge storage film provided between the plurality of electrode layers and the semiconductor body, and extending in the stacking direction. The semiconductor body includes a first portion and a second portion. The first portion is surrounded with the plurality of electrode layers and extends in a stacking direction of the stacked body. The second portion is in contact with an upper surface of the semiconductor pillar.

First claim

Opening claim text (preview).

What is claimed is: 1 . A semiconductor device, comprising: a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor pillar provided on the substrate and in the stacked body; a semiconductor body provided in the stacked body, the semiconductor body including a first portion and a second portion, the first portion surrounded with the plurality of electrode layers and extending in a stacking direction of the stacked body, the second portion in contact with an upper surface of the semiconductor pillar, a side surface of the second portion provided on the upper surface of the semiconductor pillar; and an insulating film including a charge storage film provided between the plurality of electrode layers and the semiconductor body, and extending in the stacking direction, the insulating film further including a portion separated from the semiconductor pillar via the second portion. 2 . The device according to claim 1 , wherein the first portion extends from a portion surrounded with the plurality of electrode layer to a portion surrounded with the semiconductor pillar. 3 . The device according to claim 2 , wherein the semiconductor pillar includes a damage portion provided between the semiconductor pillar and the first portion. 4 . The device according to claim 1 , further comprising a film provided on the semiconductor pillar, wherein the film is in contact with the upper surface of the semiconductor pillar and the side surface of the second portion, and is surrounded with the insulator. 5 . The device according to claim 4 , wherein the film is silicon oxide. 6 . The device according to claim 1 , wherein an upper surface of the second portion is in contact with a lower surface of the charge storage film. 7 . The device according to claim 1 , wherein the insulating film includes a cover insulating film provided between the charge storage film and the insulator, and a lower surface of the cover insulating film is in contact with the upper surface of the semiconductor pillar. 8 . The device according to claim 7 , wherein outside of a side surface of the cover insulating film is coplanar with a side surface of the semiconductor pillar. 9 . The device according to claim 1 , wherein the second portion is separated from the insulator. 10 . The device according to claim 1 , wherein, as viewed in the stacking direction, a maximum diameter of the second portion is larger than a maximum diameter of the first portion. 11 . The device according to claim 1 , wherein the semiconductor body includes a third portion extending the stacking direction, and provided between the first portion and the insulating film. 12 . The device according to claim 11 , wherein the semiconductor body includes a fourth portion provided between the third portion and the charge storage film, along the stacking direction, wherein the charge storage film is provided between the second portion and the fourth portion. 13 . The device according to claim 12 , wherein, as viewed in the stacking direction, a maximum diameter of the second portion is larger than a maximum diameter of the fourth portion. 14 . A method for manufacturing a semiconductor device, comprising: forming a stacked body on a substrate, the stacked body including a plurality of first layers stacked with an insulator interposed; forming a hole, the hole piercing the stacked body and reaching the substrate; forming a semiconductor pillar continued from an upper surface of the substrate to inside of the stacked body, the upper surface of the substrate exposed from the hole; forming an insulating film on a side wall of the hole and an upper surface of the semiconductor pillar, the insulating film including a cover insulating film formed on the side wall of the hole and the upper surface of the semiconductor pillar, and a charge storage film formed on a side surface of the cover insulating film; removing a bottom portion of the insulating film ,and forming a recess portion in the insulating film; recessing the cover insulating film exposed from the recess portion, and exposing the upper surface of the semiconductor pillar from the recess portion; and forming a semiconductor body on the upper surface of the semiconductor pillar and a side surface of the insulating film. 15 . The method according to claim 14 , wherein the removing the bottom portion of the insulating film includes removing simultaneously a portion of the semiconductor pillar with the bottom portion of the insulating film, and forming the recess portion in the semiconductor pillar. 16 . The method according to claim 14 , wherein the insulating film includes a tunneling insulating film formed between the charge storage film and the semiconductor body, the recessing the cover insulating film includes recessing simultaneously the tunneling insulating film exposed from the recess portion with the cover insulating film. 17 . A method for manufacturing a semiconductor device, comprising: forming a stacked body on a substrate, the stacked body including a plurality of first layers stacked with an insulator interposed; forming a hole, the hole piercing the stacked body and reaching the substrate; forming a semiconductor pillar continued from an upper surface of the substrate to inside of the stacked body, the upper surface of the substrate exposed from the hole; forming a film on the semiconductor pillar; forming an insulating film on a side wall of the hole and a upper surface of the film, the insulating film including a cover insulating film formed on the side wall of the hole and the upper surface of the film, and a charge storage film formed on a side surface of the cover insulating film; removing a bottom portion of the insulating film and a portion of the film ,and forming a recess portion in the insulating film and the film; recessing the film exposed from the recess portion, and exposing the upper surface of the semiconductor pillar from the recess portion; and forming a semiconductor body on the upper surface of the semiconductor pillar, a side surface of the film, and a side surface of the insulating film. 18 . The method according to claim 17 , wherein the forming of the film includes forming the film by oxidizing an upper portion of the semiconductor pillar. 19 . The method according to claim 18 , wherein the forming of the film includes forming the film by oxidizing the upper portion of the semiconductor pillar using steam generator. 20 . The method according to claim 17 , wherein the recessing the film includes recessing simultaneously the cover insulating film exposed from the recess portion with the film.

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What does patent US2017263633A1 cover?
According to the embodiment, a semiconductor device includes: a substrate; a stacked body provided on the substrate and including a plurality of electrode layers stacked with an insulator interposed; a semiconductor pillar provided on the substrate and in the stacked body; a semiconductor body provided in the stacked body; and an insulating film including a charge storage film provided between …
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H01L27/11582. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Sep 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).