Digital interconnects with protocol-agnostic repeaters

Patent metadata

Field	Value
Publication number	US-2017262402-A1
Application number	US-201715607367-A
Country	US
Kind code	A1
Filing date	May 26, 2017
Priority date	Jan 6, 2015
Publication date	Sep 14, 2017
Grant date	—

Abstract

A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

First claim

What is claimed is:

1 . A system, comprising:
a first endpoint comprising a first transmitter, a first receiver, a data copier coupled to the first receiver, a clock-signal source, and a modulation encoder coupled to the data copier and to the clock-signal source; a second endpoint comprising a second transmitter and a second receiver; a first in-line component comprising a modulation decoder and control logic to modify operation of the in-line component in response to a message; a first link segment to carry the data-stream between the first endpoint and the in-line component; a second link segment to carry the data-stream between the in-line component and the second endpoint; and a first clock channel separated from the first link segment and the second link segment to carry an encoded clock signal from the modulation encoder to the modulation decoder; wherein, in response to the first endpoint's identification of a message in the data stream to control the in-line component: the data copier copies the message to the modulation encoder; the modulation encoder embeds the message in the clock signal while preserving timing information in the clock signal, thereby forming the encoded clock signal; the encoded clock signal is transmitted to the in-line component through the first clock channel and decoded by the decoder to yield the message; and the in-line component modifies its operation in response to the message.

2 . The system of claim 1 , wherein the in-line component comprises a signal conditioner to receive, condition, and re-transmit the data-stream, and
wherein the message comprises information to control the signal conditioner.

3 . The system of claim 2 , wherein the signal conditioner comprises a re-driver, a re-timer, or both.

4 . The system of claim 2 , wherein the data-stream flows between the first endpoint and the second endpoint through the in-line component in both directions simultaneously; and
wherein the signal conditioner conditions the signals traveling in both directions.

5 . The system of claim 1 , wherein the data-stream flows to the first link segment in the second link segment at any of a plurality of data rates;
wherein the in-line component operates differently for different data rates; and wherein the message is to reconfigure the in-line component to operate at a different data rate.

6 . The system of claim 1 , wherein the message has a different protocol from a data-stream protocol.

Assignees

• Intel Corp

Inventors

• Chen Huimin
• Quiet Duane G

Classifications

• G06F13/4072 Primary

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• G06F13/4295

  using an embedded synchronisation · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F2213/0026

  PCI express · CPC title