Imaging pixels with a fully depleted charge transfer path

Patent metadata

Field	Value
Publication number	US-2017257578-A1
Application number	US-201615176317-A
Country	US
Kind code	A1
Filing date	Jun 8, 2016
Priority date	Mar 1, 2016
Publication date	Sep 7, 2017
Grant date	—

Abstract

An imaging pixel may have a fully depleted charge transfer path between a pinned photodiode and a floating diffusion region. A pinned transfer diode may be coupled between the pinned photodiode and the floating diffusion region. The imaging pixel may be formed in upper and lower substrates with an interconnect layer coupling the upper substrate to the lower substrate. The imaging pixel may include one or more storage diodes coupled between the transfer diode and the floating diffusion region. The imaging pixel may be used to capture high dynamic range images with flicker mitigation, images synchronized with light sources, or for high frame rate operation.

First claim

What is claimed is:

1 . An imaging pixel comprising:
a pinned photodiode with a first potential; a pinned transfer diode with a second potential, wherein the second potential is higher than the first potential; a floating diffusion region with a third potential, wherein the third potential is higher than the second potential; a first transfer transistor coupled between the pinned photodiode and the pinned transfer diode; and a second transfer transistor coupled between the pinned transfer diode and the floating diffusion region, wherein the first transfer transistor, the pinned transfer diode, and the second transfer transistor form a fully depleted charge transfer path between the pinned photodiode and the floating diffusion region.

2 . The imaging pixel defined in claim 1 , wherein the pinned photodiode and pinned transfer diode are formed in an upper substrate, wherein the floating diffusion region is formed in a lower substrate, and wherein the imaging pixel further comprises an interconnect layer that couples the upper substrate to the lower substrate.

3 . The imaging pixel defined in claim 2 , wherein the interconnect layer is formed in an opaque dielectric layer.

4 . The imaging pixel defined in claim 2 , further comprising:
an additional pinned transfer diode that is formed in the lower substrate, wherein the interconnect layer couples the pinned transfer diode in the upper substrate to the additional pinned transfer diode in the lower substrate.

5 . The imaging pixel defined in claim 4 , wherein the additional pinned transfer diode has a fourth potential that is higher than the second potential and lower than the third potential.

6 . The imaging pixel defined in claim 5 , further comprising:
a storage diode with a fifth potential, wherein the fifth potential is higher than the fourth potential and lower than the third potential, wherein the second transfer transistor is coupled between the additional pinned transfer diode and the storage diode; and a third transfer transistor coupled between the storage diode and the floating diffusion region.

7 . The imaging pixel defined in claim 6 , wherein the first transfer transistor is configured to transfer charge from the pinned photodiode to the pinned transfer diode when asserted, wherein the second transfer transistor is configured to transfer charge from the additional pinned transfer diode to the storage diode when asserted, and wherein the third transfer transistor is configured to transfer charge from the storage diode to the floating diffusion region when asserted.

8 . The imaging pixel defined in claim 6 , wherein the storage diode is a first storage diode, the imaging pixel further comprising:
a second storage diode; a fourth transfer transistor coupled between the additional pinned transfer diode and the second storage diode; and a fifth transfer transistor coupled between the second storage diode and the floating diffusion region.

9 . The imaging pixel defined in claim 8 , further comprising:
a third storage diode; a sixth transfer transistor coupled between the additional pinned transfer diode and the third storage diode; and a seventh transfer transistor coupled between the third storage diode and the floating diffusion region.

10 . The imaging pixel defined in claim 8 , wherein the first and second storage diodes have different sizes.

11 . The imaging pixel defined in claim 8 , further comprising:
at least one additional pinned photodiode that is configured to share the pinned transfer diode with the pinned photodiode.

12 . The imaging pixel defined in claim 4 , wherein the interconnect layer comprises a metal layer that shields the additional pinned transfer diode and the floating diffusion region from incident light, and wherein the metal layer acts as a reflector for incident light.

13 . The imaging pixel defined in claim 1 , wherein the first transfer transistor has a circular gate that laterally surrounds the pinned transfer diode.

14 . The imaging pixel defined in claim 1 , further comprising:
a plurality of additional pinned photodiodes; and a plurality of additional transfer transistors, wherein each transfer transistor of the plurality of additional transfer transistors is coupled between a respective pinned photodiode of the plurality of additional pinned photodiodes and the pinned transfer diode.

15 . A method of operating an imaging pixel, wherein the imaging pixel comprises a pinned photodiode, a first pinned transfer diode, a second pinned transfer diode, an interconnect layer that couples the first pinned transfer diode to the second pinned transfer diode, a storage diode, a floating diffusion region, a first transfer transistor coupled between the pinned photodiode and the first pinned transfer diode, a second transfer transistor coupled between the second pinned transfer diode and the storage diode, a third transfer transistor coupled between the storage diode and the floating diffusion region, a reset transistor that is coupled between the floating diffusion region and a bias voltage, and a shutter gate that is coupled between the second pinned transfer diode and the bias voltage, the method comprising:
resetting the pinned photodiode, the first pinned transfer diode, the second pinned transfer diode, the storage diode, and the floating diffusion region by asserting the first transfer transistor, the third transfer transistor, the shutter gate, and the reset transistor; and with the photodiode, accumulating charge over a total exposure time that is split into multiple integration periods, wherein the multiple integration periods are non-continuous and are each shorter than the total exposure time, wherein the charge that is accumulated in each integration period of the multiple integration periods is transferred to the storage diode.

16 . The method defined in claim 15 , the method further comprising:
after each integration period of the multiple integration periods, clearing charge from the pinned photodiode, the first pinned transfer diode, and the second pinned transfer diode by asserting the first transfer transistor and the shutter gate.

17 . A method of operating an imaging pixel, wherein the imaging pixel comprises a pinned photodiode, a first pinned transfer diode, a second pinned transfer diode, an interconnect layer that couples the first pinned transfer diode to the second pinned transfer diode, a first storage diode, a second storage diode, and a third storage diode, a floating diffusion region, a first transfer transistor coupled between the pinned photodiode and the first pinned transfer diode, a second transfer transistor coupled between the second pinned transfer diode and the first storage diode, a third transfer transistor coupled between the first storage diode and the floating diffusion region, a fourth transfer transistor coupled between the second pinned transfer diode and the second storage diode, a fifth transfer transistor coupled between the second storage diode and the floating diffusion region, a sixth transfer transistor coupled between the second pinned transfer diode and the third storage diode, a seventh transfer transistor coupled between the third storage diode and the floating diffusion region, a reset transistor that is coupled between the floating diffusion region and a bias voltage, and a shutter gate that is coupled between the second pinned transfer diode and the bias voltage, the method comprising:
resetting the pinned photodiode, the first pinned transfer diode, the second pinned transfer diode, the

Assignees

• Semiconductor Components Ind Llc

Inventors

• Velichko Sergey
• Korobov Vladimir

Classifications

• H04N25/589 Primary

  with different integration times, e.g. short and long exposures · CPC title

• H04N25/587

  acquired sequentially, e.g. using the combination of odd and even image fields · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N25/616

  involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling · CPC title