Measurement system having a digital edge trigger detection circuit that is capable of operating at the full signal bandwidth of the measurement system

Patent metadata

Field	Value
Publication number	US-2017254835-A1
Application number	US-201715396666-A
Country	US
Kind code	A1
Filing date	Jan 1, 2017
Priority date	Mar 1, 2016
Publication date	Sep 7, 2017
Grant date	—

Abstract

A measurement system is provided that has a digital edge trigger circuit that is capable of operating at the full signal bandwidth of the measurement system. The digital edge trigger circuit comprises a plurality of processors that process time-interleaved digital data samples output from respective time-interleaved ADCs to perform edge trigger detection. The processors share edge detection information with one another to increase the speed at which edge trigger detection is performed to enable the digital edge trigger circuit to operate at the full signal bandwidth of the measurement system.

First claim

What is claimed is:

1 . A measurement system comprising:
N time-interleaved analog-to-digital converters (ADCs) that receive and sample a time-varying waveform to produce N digital data sets, respectively, where N is a positive integer that is equal to or greater than 2, each digital data set comprising digital data samples that are time-interleaved with the digital data samples of the other digital data sets; and a digital edge trigger system comprising N processors, each processor receiving a respective digital data set and performing an edge trigger detection algorithm that processes the respective digital data set to determine whether a respective early sample in time that is below a lower threshold value, TH L , exists, to determine whether a respective late sample in time that is below TH L or above a higher threshold value, TH H , exists, and to determine whether a respective early sample in time that is above TH H exists, the processors sharing information regarding any early samples in time below TH L , any late samples in time below TH L or above TH H , and any early samples in time above TH H to determine whether a trigger threshold level crossing has been detected.

2 . The measurement system of claim 1 , wherein at least one of the processors determines, based on the shared information, which early sample in time below TH L , if any exists, is the earliest sample in time below TH L , which late sample in time below TH L or above TH H , if any exists, is the latest sample in time below TH L or above TH H , and which early sample in time above TH H , if any exists, is the earliest sample in time above TH H , and wherein said at least one processor uses the earliest sample in time below TH L , the latest sample in time below TH L or above TH H , and the earliest sample in time above TH H and after the earliest sample in time below TH L to determine whether a trigger threshold level crossing has been detected.

3 . The measurement system of claim 2 , wherein the processors are connected in a daisy chain configuration such that each processor is connected to two adjacent processors, and wherein said at least one of the processors functions as a master processor of the daisy chain configuration.

4 . The measurement system of claim 3 , wherein each processor includes first and second serializer/deserializer (SERDES) interfaces that are connected to the first and second SERDES interfaces, respectively, of at least one of the other processors to form the daisy chain interconnection among the processors.

5 . The measurement system of claim 2 , wherein said at least one processor is a master processor and is connected directly to all of the other processors.

6 . The measurement system of claim 5 , wherein each processor includes at least one serializer/deserializer (SERDES) interface that is connected to a respective SERDES interface of the master processor.

7 . The measurement system of claim 2 , wherein the information that is shared among the processors includes an index identifying when a sample occurred in time.

8 . The measurement system of claim 7 , wherein the information that is shared among the processors includes at least one bit indicating whether or not an early sample in time below TH L exists.

9 . The measurement system of claim 8 , wherein the information that is shared among the processors includes at least one bit indicating whether or not an early sample in time above TH H exists.

10 . The measurement system of claim 9 , wherein the information that is shared among the processors includes at least one bit indicating whether or not a late sample in time below TH L or above TH H exists.

11 . The measurement system of claim 2 , wherein at least one of the processors acts as a master processor, and wherein the master processor determines whether the latest sample in time below TH L or above TH H in a previous time slot is below TH L , and if so, determines that a trigger threshold level crossing has been detected in a current time slot if an earliest sample in time in the current time slot above TH H exists, and wherein if the master processor determines that the latest sample in time below TH L or above TH H in the previous time slot is above TH H , the master processor determines that a trigger threshold level crossing has been detected in the current time slot if an earliest sample in time in the current time slot above TH H and later in time than the earliest sample below TH L in the current time slot exists, and wherein if the master processor determines that a trigger threshold crossing has been detected, the master processor decides that the trigger threshold level crossing occurred at some instant in time in between the earliest sample above TH H and a sample that immediately preceded the earliest sample above TH H in time.

12 . The measurement system of claim 11 , wherein if the master processor determines that a trigger threshold level crossing occurred, the master processor performs an estimation algorithm that estimates that the trigger threshold level crossing occurred at an instant in time one-half way in between an instant in time when the earliest sample above TH H occurred and an instant in time when the sample occurred that immediately preceded the earliest sample above TH H .

13 . The measurement system of claim 11 , wherein if the master processor determines that a trigger threshold level crossing occurred, the master processor performs an interpolation algorithm that interpolates an instant in time in between an instant in time when the earliest sample above TH H occurred and an instant in time when the sample occurred that immediately preceded the earliest sample above TH H as being the instant in time when the trigger threshold level crossing occurred.

14 . The measurement system of claim 1 , wherein the digital trigger system operates at a full signal bandwidth of the measurement system.

15 . A measurement system comprising:
N time-interleaved analog-to-digital converters (ADCs), the ADCs sampling a time-varying waveform at instants in time that are offset from one another in time to produce N respective digital data sets that are time-interleaved, each digital data set comprising digital data samples, and wherein N is a positive integer that is equal to or greater than 2; and N processors, each processor being interconnected with a respective ADC to receive a respective digital data set from the respective ADC, the processors being connected in a daisy chain configuration such that each processor communicates with at least one adjacent processor in the daisy chain configuration, and wherein each processor performs an edge trigger detection algorithm that processes the respective digital data set to determine whether a respective early sample in time that is below a lower threshold value, TH L , exists, to determine whether a respective late sample in time that is below TH L or above a higher threshold value, TH H , exists, and to determine whether a respective early sample in time that is above TH H exists, the processors sharing information, via the daisy chain configuration, regarding any early samples in time below TH L , any late samples in time below TH L or above TH H , and any early samples in time above TH H to determine which early sample in time below TH L , if any exists, is the earliest sample in time below TH L , which late sample in time below TH L or above TH H , if any exists, is the latest sample in time below TH L or above TH H , and which early sample in time above TH H , if any exists, is the earliest sample in time abov

Assignees

• Keysight Technologies Inc

Inventors

• Montijo Allen

Classifications

• G01R13/0272

  for sampling · CPC title

• G01R31/3173 Primary

  Marginal testing · CPC title

• G01R13/0254 Primary

  for triggering, synchronisation · CPC title