Low stress vias

Patent metadata

Field	Value
Publication number	US-2017250132-A1
Application number	US-201715597699-A
Country	US
Kind code	A1
Filing date	May 17, 2017
Priority date	Jul 29, 2011
Publication date	Aug 31, 2017
Grant date	—

Abstract

A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

First claim

1 . A method of fabricating a component, comprising:
forming an opening extending from a rear surface of a substrate towards a front surface of the substrate remote therefrom, the opening defining an inner surface between the front and rear surfaces, the substrate consisting essentially of a material having a CTE less than 10 ppm/° C.; and forming a conductive via including forming a first metal layer overlying the inner surface of the opening and forming a second metal region overlying the first metal layer and electrically coupled to the first metal layer, the second metal region having a CTE greater than a CTE of the first metal layer, the conductive via having an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

2 . A method as claimed in claim 1 , wherein the step of forming the opening includes performing a first anisotropic etch process to produce an initial inner surface and a second process to smooth the initial inner surface to become the inner surface, the first anisotropic etch process and the second process producing a transition surface between the opening and at least one of the front or rear surfaces, wherein a radius of the transition surface is greater than 5% of a radius of the opening.

3 . A method as claimed in claim 1 , wherein the substrate further includes a plurality of conductive elements at the front surface, at least one of the conductive elements being electrically connected with the conductive via, wherein the substrate embodies a plurality of active semiconductor devices electrically connected with at least some of the conductive elements.

4 . A method as claimed in claim 3 , wherein the first metal layer is formed in contact with a bottom surface of one of the conductive elements.

5 . A method as claimed in claim 1 , further comprising, before forming the conductive via, depositing an insulating dielectric layer coating an inner surface of the opening, the dielectric layer separating and insulating the first metal layer and the second metal region from the substrate at least within the opening.

6 . A method as claimed in claim 1 , wherein the second metal region occupies at most 80% of a diameter of the opening in a lateral direction parallel to the front surface of the substrate.

7 . A method as claimed in claim 1 , wherein the first metal layer has a surface that conforms to a contour of an inner surface of the opening.

8 . A method as claimed in claim 1 , further comprising forming a conductive contact exposed at the rear surface for interconnection with an external element, the conductive contact being electrically connected with the first metal layer and the second metal region.

9 . A method as claimed in claim 1 , further comprising, before forming the first metal layer, forming a barrier metal layer overlying the insulating dielectric layer, the barrier metal layer being a metal different than the metals of the first metal layer and the second metal region, wherein the first metal layer is formed overlying the barrier metal layer.

10 . A method as claimed in claim 1 , wherein the first metal layer includes a portion overlying an axially facing surface of the second metal region.

11 . A method as claimed in claim 10 , wherein the first metal layer completely surrounds the second metal region.

12 . A method as claimed in claim 1 , wherein the second metal region is made of a porous metal and includes voids therein.

13 . A method as claimed in claim 12 , wherein the second metal region is formed by dendrite plating.

14 . A method as claimed in claim 12 , further comprising depositing a dielectric layer overlying a top surface of the second metal region.

15 . A method as claimed in claim 1 , further comprising, before forming the second metal region, depositing a foam or fibrous material overlying the first metal layer, wherein the second metal region is formed within open cells within the foam or fibrous material.

16 . A method as claimed in claim 15 , further comprising, after forming the second metal region, removing the foam or fibrous material.

17 . A method of fabricating a component, comprising:
forming an opening extending from a rear surface of a substrate towards a front surface of the substrate remote therefrom, the opening defining an inner surface between the front and rear surfaces, the substrate consisting essentially of a material having a CTE less than 10 ppm/° C.; and forming a conductive via within the opening including forming a metal region overlying the inner surface, the metal region having cavities trapped therein.

18 . A method as claimed in claim 17 , wherein the step of forming the conductive via further includes, before forming the metal region, forming a barrier metal layer overlying the inner surface, the metal region being formed overlying the barrier metal layer, the barrier metal layer being a metal different than the metal of the metal region.

19 . A method as claimed in claim 18 , wherein the metal region is a first metal region and the barrier metal layer is a first barrier metal layer, wherein the step of forming the conductive via further includes, after forming the first barrier metal layer, forming a second metal layer overlying the first barrier metal layer and forming a third barrier metal layer overlying the second metal layer, the second metal region being formed overlying the third barrier metal layer.

20 . A method as claimed in claim 17 , further comprising forming a conductive contact exposed at the rear surface for interconnection with an external element, the conductive contact being electrically connected with the first metal layer and the second metal region.

21 . A method as claimed in claim 17 , further comprising, before forming the metal region, forming an insulating dielectric layer coating an inner surface of the opening, the dielectric layer separating and insulating the conductive via from the substrate at least within the opening.

Assignees

• Tessera Inc

Inventors

• Mohammed Ilyas
• Haba Belgacem
• Uzoh Cyprian Emeka

Classifications

• H10W72/285

  Alignment aids, e.g. alignment marks · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/023 Primary

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title