Semiconductor apparatus comprising a plurality of current sink units

Patent metadata

Field	Value
Publication number	US-2017236583-A1
Application number	US-201715583543-A
Country	US
Kind code	A1
Filing date	May 1, 2017
Priority date	Aug 22, 2013
Publication date	Aug 17, 2017
Grant date	—

Abstract

A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.

First claim

What is claimed is:

1 . A processor, comprising:
a processor configured to interpret a command input from the outside and control an operation of information according to an interpretation result of the command; an auxiliary storage device configured to store a program for interpretation of the command, and the information; a main storage device configured to transfer the program and information from the auxiliary storage device and store the program and the information so that the processor performs the operation using the program and information when the program is executed; and an interface device configured to perform communication between the outside and one or more among the processor, the auxiliary storage device, and the main storage device, wherein at least one of the auxiliary storage device and the main storage device includes a semiconductor memory apparatus comprising: a driving driver unit configured to provide voltages with different voltage levels to a plurality of respective resistive memory elements in response to a column select signal; a plurality of current sink units configured to flow current from one of the plurality of resistive memory elements to a ground terminal in response to a plurality of word line select signals; and a sink current control unit configured to control the plurality of current sink units to flow different amounts of current from the plurality of current sink units to the ground terminal.

2 . The semiconductor memory apparatus according to claim 1 ,
wherein the driving driver unit comprises: a driving driver configured to provide a driving voltage in response to the column select signal; and a plurality of resistor elements electrically coupled in series to be inputted with an output of the driving driver, and wherein the resistive memory elements are electrically coupled to respective nodes where the plurality of resistor elements are electrically coupled.

3 . The semiconductor memory apparatus according to claim 2 ,
wherein the plurality of current sink units are electrically coupled to the plurality of respective resistive memory elements, and wherein one of the plurality of current sink units is activated in response to the plurality of word line select signals.

4 . The semiconductor memory apparatus according to claim 3 , wherein the current sink control unit differentiates amounts of current flowed by the plurality of current sink units electrically coupled to the plurality of respective resistive memory elements, according to respective distances between the driving driver and the plurality of resistive memory elements.

5 . The semiconductor memory apparatus according to claim 4 , wherein the current sink control unit is configured such that an amount of current flowed from a current sink unit electrically coupled with a resistive memory element close to the driving driver, to the ground terminal, is smaller than an amount of current flowed from a current sink unit electrically coupled with a resistive memory element distant from the driving driver.

6 . The semiconductor memory apparatus according to claim 5 ,
wherein the current sink control unit comprises a plurality of resistor elements which are electrically coupled in series, and wherein the plurality of resistor elements are respectively electrically coupled to the plurality of current sink units, and the ground terminal is electrically coupled to a resistor element which is farthest from the driving driver.

Assignees

• Sk Hynix Inc

Inventors

• Yoon Jung Hyuk
• Shin Yoon Jae

Classifications

• G11C11/1653

  Address circuits or decoders · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0028 Primary

  Word-line or row circuits · CPC title

• G11C13/0038

  Power supply circuits · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title