Synchronous slave-to-slave communications

Patent metadata

Field	Value
Publication number	US-2017222829-A1
Application number	US-201715411706-A
Country	US
Kind code	A1
Filing date	Jan 20, 2017
Priority date	Jan 29, 2016
Publication date	Aug 3, 2017
Grant date	—

Abstract

Disclosed herein are systems and techniques for slave-to-slave communication in a multi-node, daisy-chained network. Slave nodes may provide or receive upstream or downstream data directly to/from other slave nodes, without the need for data slots first to route through the master node.

First claim

1 . A low latency communication system, comprising:
a slave node transceiver, including: upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device, downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device, and a peripheral device interface to receive data from a peripheral device communicatively coupled to the peripheral device interface, wherein the downstream transceiver circuitry is to include the data in the third signal.

2 . The low latency communication system of claim 1 , wherein the data is audio data.

3 . The low latency communication system of claim 1 , wherein the first signal includes data generated by a peripheral device communicatively coupled to the upstream device, the third signal is provided downstream subsequent to receipt of the first signal, and the third signal includes less than all of the data generated by the peripheral device communicatively coupled to the upstream device.

4 . The low latency communication system of claim 3 , wherein the upstream device is a host device.

5 . The low latency communication system of claim 3 , wherein the upstream device is a master node.

6 . The low latency communication system of claim 3 , wherein the upstream device is a slave node.

7 . The low latency communication system of claim 3 , wherein the peripheral device interface is to provide, to the peripheral device communicatively coupled to the peripheral device interface, at least some of the data generated by the peripheral device communicatively coupled to the upstream device.

8 . The low latency communication system of claim 3 , wherein an intervening upstream device is disposed along the two-wire bus in a daisy chain between the slave node transceiver and the upstream device.

9 . The low latency communication system of claim 1 , wherein the fourth signal includes data generated by a peripheral device communicatively coupled to the downstream device, the second signal is provided upstream subsequent to receipt of the fourth signal, and the second signal includes less than all of the data generated by the peripheral device communicatively coupled to the downstream device.

10 . The low latency communication system of claim 9 , wherein the peripheral device interface is to provide, to the peripheral device communicatively coupled to the peripheral device interface, at least some of the data generated by the peripheral device communicatively coupled to the downstream device.

11 . The low latency communication system of claim 9 , wherein the peripheral device includes a speaker.

12 . The low latency communication system of claim 9 , wherein an intervening downstream device is disposed along the two-wire bus in a daisy chain between the slave node transceiver and the downstream device.

13 . The low latency communication system of claim 1 , further comprising the upstream device and the downstream device.

14 . The low latency communication system of claim 1 , wherein the slave node transceiver further includes:
clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the slave node transceiver is based on the clock signal.

15 . The low latency communication system of claim 14 , wherein the second signal includes a synchronization response frame and the synchronization response frame is associated with upstream data in a superframe of the second signal.

16 . The low latency communication system of claim 1 , further comprising the peripheral device.

17 . A low latency communication system, comprising:
a master node transceiver; and a plurality of slave node transceivers communicatively coupled to each other and to the master note transceiver in a daisy chain two-wire bus, wherein at least one of the slave node transceivers includes: upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device along the bus and to provide a second signal over the two-wire bus to the upstream device, wherein the first signal includes data generated by a peripheral device communicatively coupled to the upstream device, and downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device on the bus and to receive a fourth signal over the two-wire bus from the downstream device, wherein the third signal is provided downstream subsequent to receipt of the first signal, and the third signal includes less than all of the data generated by the peripheral device communicatively coupled to the upstream device.

18 . The low latency communication system of claim 17 , further comprising:
a host device communicatively coupled to the master node transceiver.

19 . A method of slave-to-slave communication in a two-wire daisy chain bus, comprising:
receiving, at a first slave device, data from a second slave device downstream from the first slave device over the bus; and providing, by the first slave device to a third device upstream from the first slave device over the bus, less than all of the data from the second slave device.

20 . The method of claim 19 , wherein the data from the second slave device is data generated by a peripheral device communicatively coupled to the second slave device via an Inter-Integrated Circuit Sound (I2S) transceiver, a Time Division Multiplex (TDM) transceiver, a Pulse Density Modulation (PDM) transceiver, an Inter-Integrated Circuit (I2C) transceiver, or a General Purpose Input/Output (GPIO) pin.

Assignees

• Analog Devices Inc

Inventors

• Kessler Martin
• Hooper William
• Lahr Lewis F

Classifications

• G06F13/40

  Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} · CPC title

• H04L12/40039 Primary

  Details regarding the setting of the power status of a node according to activity on the bus · CPC title

• H04L12/40156

  by using dedicated slots associated with a priority level · CPC title

• G06F13/4247

  on a daisy chain bus · CPC title

• H04L12/43 Primary

  with synchronous transmission, e.g. time division multiplex [TDM], slotted rings · CPC title