A display device and a driving method

Patent metadata

Field	Value
Publication number	US-2017221428-A1
Application number	US-201615325052-A
Country	US
Kind code	A1
Filing date	Feb 18, 2016
Priority date	Sep 2, 2015
Publication date	Aug 3, 2017
Grant date	—

Abstract

The present application discloses a display device and a driving method. The display device comprises: a power reset circuit and a source drive chip for driving a display panel to display. An input terminal of the power reset circuit is connected with a power signal output terminal, a control terminal of the power reset circuit is connected with a reset signal terminal, an output terminal of the power reset circuit is connected with a power signal input terminal of the source drive chip. The power reset circuit is used for resetting a power signal synchronously when receiving a reset signal, and inputting the reset power signal into the power signal input terminal of the source drive chip.

First claim

1 . A display device, comprising: a power reset circuit and a source drive chip for driving a display panel to display; wherein,
an input terminal of the power reset circuit is connected with a power signal output terminal, a control terminal of the power reset circuit is connected with a reset signal terminal, an output terminal of the power reset circuit is connected with a power signal input terminal of the source drive chip; the power reset circuit is used for resetting a power signal synchronously when receiving a reset signal, and inputting the reset power signal into the power signal input terminal of the source drive chip.

2 . The display device as claimed in claim 1 , wherein the power reset circuit comprises: a first switch transistor, a second switch transistor, a first resistor and a second resistor; wherein,
a gate of the first switch transistor is connected with the reset signal output terminal, a source of the first switch transistor is connected with one terminal of the first resistor and a gate of the second switch transistor respectively, a drain of the first switch transistor is connected with a ground level signal terminal; the other terminal of the first resistor is connected with the power signal output terminal and a source of the second switch transistor respectively; a drain of the second switch transistor is connected with one terminal of the second resistor and the power signal input terminal of the power driver chip respectively; the other terminal of the second resistor is connected with the ground level signal terminal.

3 . The display device as claimed in claim 2 , wherein the source drive chip comprises: a status register; wherein,
the status register is used for outputting a first characterization value characterizing that the source drive chip is in an abnormal operating state when the source drive chip has electrostatic abnormity, and outputting a second characterization value characterizing that the source drive chip is in a normal operating state when the source drive chip operates normally.

4 . The display device as claimed in claim 3 , further comprising: a control unit; wherein,
the control unit is used for reading characterization values of the status register at every preset time interval; inputting a reset signal to the control terminal of the power reset circuit when reading the first characterization value, and not inputting the reset signal to the control terminal of the power reset circuit when reading the second characterization value.

5 . The display device as claimed in claim 4 , wherein the control unit is further used for inputting the reset signal to the reset terminal of the source drive chip when reading the first characterization value.

6 . The display device as claimed in claim 5 , wherein the power reset circuit and the control unit are arranged on a flexible circuit board.

7 . A power signal reset driving method for use in a display device as claimed in claim 1 , comprising:
when receiving a reset signal, the power reset circuit resetting a power signal synchronously, and inputting the reset power signal into the power signal input terminal of the source drive chip.

8 . The method as claimed in claim 7 , further comprising:
reading characterization values characterizing the operating states of the source drive chip at every preset time interval; inputting the reset signal to the control terminal of the power reset circuit after it is determined that the source drive chip has electrostatic abnormity.

9 . The method as claimed in claim 8 , wherein reading characterization values characterizing the operating states of the source drive chip comprises:
reading a first characterization value characterizing that the source drive chip is in an abnormal operating state when the source drive chip has electrostatic abnormity, and reading a second characterization value characterizing that the source drive chip is in a normal operating state when the source drive chip operates normally.

10 . The method as claimed in claim 9 , wherein inputting the reset signal to the control terminal of the power reset circuit after it is determined that the source drive chip has electrostatic abnormity comprises:
inputting the reset signal to the control terminal of the power reset circuit when reading the first characterization value, and not inputting the reset signal to the control terminal of the power reset circuit when reading the second characterization value.

11 . The method as claimed in claim 10 , further comprising: inputting the reset signal to the reset terminal of the source drive chip when reading the first characterization value.

12 . The method as claimed in claim 7 , wherein the power reset circuit comprises: a first switch transistor, a second switch transistor, a first resistor and a second resistor; wherein,
a gate of the first switch transistor is connected with the reset signal output terminal, a source of the first switch transistor is connected with one terminal of the first resistor and a gate of the second switch transistor respectively, a drain of the first switch transistor is connected with a ground level signal terminal; the other terminal of the first resistor is connected with the power signal output terminal and a source of the second switch transistor respectively; a drain of the second switch transistor is connected with one terminal of the second resistor and the power signal input terminal of the power driver chip respectively; the other terminal of the second resistor is connected with the ground level signal terminal.

13 . The method as claimed in claim 12 , wherein the source drive chip comprises: a status register; wherein,
the status register is used for outputting a first characterization value characterizing that the source drive chip is in an abnormal operating state when the source drive chip has electrostatic abnormity, and outputting a second characterization value characterizing that the source drive chip is in a normal operating state when the source drive chip operates normally.

14 . The method as claimed in claim 13 , further comprising: a control unit; wherein,
the control unit is used for reading characterization values of the status register at every preset time interval; inputting a reset signal to the control terminal of the power reset circuit when reading the first characterization value, and not inputting the reset signal to the control terminal of the power reset circuit when reading the second characterization value.

15 . The method as claimed in claim 14 , wherein the control unit is further used for inputting the reset signal to the reset terminal of the source drive chip when reading the first characterization value.

16 . The method as claimed in claim 15 , wherein the power reset circuit and the control unit are arranged on a flexible circuit board.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Wang Xiurong
• Gao Bo
• Shi Lingyun
• Zhang Hao
• Li Yafei
• Han Peng
• Meng Chen
• Xue Zijiao
• Shi Tiankuo
• He Quanhua

Classifications

• G09G2330/08

  Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared · CPC title

• G09G2330/06

  Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation · CPC title

• G09G2330/04

  Display protection · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/061

  for resetting or blanking · CPC title