Testing a data coherency algorithm

Patent metadata

Field	Value
Publication number	US-2017220439-A1
Application number	US-201615197534-A
Country	US
Kind code	A1
Filing date	Jun 29, 2016
Priority date	Jan 29, 2016
Publication date	Aug 3, 2017
Grant date	—

Abstract

Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.

First claim

What is claimed is:

1 . A method of testing a data coherency algorithm of a multi-processor environment, wherein a simulated multi-processor environment containing a private cache hierarchy and simulation drivers for other components of the multi-processor environment is provided, the method comprising:
implementing a global time incremented on a processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing atomicity and coherency of currently executed instructions; implementing a transactional footprint, the transactional footprint keeping an address of each cache line that was used by the processor core, while the processor core is guaranteeing the atomicity and coherency of a transaction; implementing a reference model, the reference model operating on a cache line and keeping a set of timestamps for the cache line, the set comprising a construction date representing a first global timestamp when new data arrives at the private cache hierarchy, and an expiration date representing a second global timestamp when the private cache hierarchy is hit by a cross-invalidation; implementing a core observed timestamp representing a global timestamp, which is an oldest construction date of data used before; implementing interface events that monitor at least one of:
a fetch return from the simulated multi-processor environment to update the construction date;
a fetch return from an L1 cache to the processor core to update the core observed timestamp;
a cross-invalidate from the simulated multi-processor environment to update the expiration date;
a transaction start instruction being executed by the processor core to update the transactional execution flag and clear the transactional footprint; or
a transaction end instruction being executed by the processor core to perform the checking; and
reporting an error based on detecting a transaction end event and finding a cache line in the transactional footprint with an expiration date that is older than or equal to a core observed time.

2 . The method according to claim 1 , wherein the set further comprises a potential construction date representing a third global timestamp when new data arrives at the private cache hierarchy, and a confirmed construction date representing a fourth global timestamp confirming usage of new data by the processor core; and
wherein the interface events further monitor at least one of:
a fetch return from the simulated multi-processor environment to update the potential construction date; or
a fetch return from an L2 cache to the L1 cache to update the confirmed construction date.

3 . The method according to claim 2 , further comprising reporting an error based on data being used with an expiration date that is older than or equal to the core observed time.

4 . The method according to claim 2 , further comprising based on the fetch return from the simulated multi-processor environment, updating the potential construction date in the reference model with the global time.

5 . The method according to claim 2 , further comprising based on a missed fetch return from the L2 cache to the L1 cache, updating the confirmed construction date in the reference model with the potential construction date of the cache line.

6 . The method according to claim 2 , further comprising based on a fetch return from the L1 cache to the processor core, updating the core observed timestamp with the confirmed construction date of the cache line.

7 . The method according to claim 2 , further comprising based on a cross-invalidate from the simulated multi-processor environment, updating the expiration date in the reference model with the global time.

8 . The method according to claim 1 , further comprising based on a fetch return from the simulated multi-processor environment, updating the construction date in the reference model with the global time.

9 . The method according to claim 1 , further comprising based on a fetch return from the L1 cache to the processor core, checking for the transactional execution flag.

10 . The method according to claim 1 , further comprising based on a fetch return from the L1 cache to the processor core, adding a cache line to the transactional footprint.

11 . The method according to claim 1 , further comprising based on a fetch return from the L1 cache to the processor core, updating the core observed timestamp with the construction date.

12 . The method according to claim 1 , further comprising based on a cross-invalidate from the simulated multi-processor environment, updating the expiration date in the reference model with the global time.

13 . The method according to claim 1 , further comprising based on the transaction end instruction, setting the transactional execution flag to false.

Assignees

• IBM

Inventors

• Habermann Christian
• Koch Gerrit
• Recktenwald Martin
• Winkelmann Ralf

Classifications

• G06F12/0837

  with software control, e.g. non-cacheable data · CPC title

• G06F11/0724 Primary

  in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F11/1474

  in transactions (updating of structured data in databases G06F16/23) · CPC title

• G06F11/261

  by simulating additional hardware, e.g. fault simulation · CPC title