Power monitoring calibration to a target performance level

Patent metadata

Field	Value
Publication number	US-2017220362-A1
Application number	US-201615008558-A
Country	US
Kind code	A1
Filing date	Jan 28, 2016
Priority date	Jan 28, 2016
Publication date	Aug 3, 2017
Grant date	—

Abstract

Systems and methods for performing power monitoring calibration to a target performance level are described. In some embodiments, an Information Handling System (IHS) may include a plurality of Central Processing Units (CPUs) and a logic circuit coupled to the plurality of CPUs, the logic circuit configured to: measure an operating performance level for each of the plurality of CPUs under a controlled workload and, in response to a determination that the operating performance level of any given one of the CPUs does not match a target performance level for all of the CPUs, apply an offset to a voltage regulator measurement associated with the given CPU that causes the operating performance level of the given CPU to match the target performance level for all of the CPUs.

First claim

1 . An Information Handling System (IHS), comprising:
a plurality of Central Processing Units (CPUs); and a logic circuit coupled to the plurality of CPUs, the logic circuit configured to:
measure an operating performance level for each of the plurality of CPUs under a controlled workload; and
in response to a determination that the operating performance level of any given one of the CPUs does not match a target performance level for all of the CPUs, apply an offset to a voltage regulator measurement associated with the given CPU that causes the operating performance level of the given CPU to match the target performance level for all of the CPUs.

2 . The IHS of claim 1 , wherein the logic circuit is a Basic Input/Output System (BIOS).

3 . The IHS of claim 2 , wherein the BIOS is configured to measure the operating performance in response to an SMI (System Management Interrupt) issued by a Baseboard Management Controller (BMC).

4 . The IHS of claim 2 , wherein the operating performance level of the given CPU is below the target performance level for all of the CPUs, and wherein the offset has a negative value.

5 . The IHS of claim 4 , wherein the offset compensates for the IHS's otherwise over reporting of the operating performance level of the given CPU.

6 . The IHS of claim 2 , wherein the operating performance level of the given CPU is above the target performance level for all of the plurality of CPUs, and wherein the offset has a positive value.

7 . The IHS of claim 6 , wherein the offset compensates for the IHS's otherwise under reporting of the operating performance level of the given CPU.

8 . The IHS of claim 2 , wherein to apply the offset the BIOS is configured to write the offset to an output current (I OUT ) measurement of a Power Management Bus (PMBus)-enabled voltage regulator using a Host Embedded Controller Interface (HECI)-to-PMBus proxy.

9 . The IHS of claim 1 , wherein the logic circuit is a Baseboard Management Controller (BMC), and wherein to apply the offset the BMC is configured to write the offset to an output current (I OUT ) measurement of a Power Management Bus (PMBus)-enabled voltage regulator using a Intelligent Platform Management Bus (IPMB)-to-PMBus proxy.

10 . The IHS of claim 1 , the logic circuit further configured to remove the offset from the voltage regulator measurement associated with the given CPU in response to a user's request to report the operating performance level of the given CPU.

11 . The IHS of claim 1 , wherein the offset is selected to maintain a power consumed by the given CPU within a reporting error band indicated by a manufacturer to the CPU for the operating performance level.

12 . The IHS of claim 1 , wherein the target performance level for all of the CPUs is an average of the operating performance levels of all of the CPUs.

13 . The IHS of claim 1 , wherein the target performance level for all of the CPUs is a highest of the operating performance levels of all of the CPUs.

14 . The IHS of claim 1 , wherein the target performance level for all of the CPUs further includes other CPUs of a plurality of other IHSs in a server cluster.

15 . A memory device having program instructions stored thereon that, upon execution, cause an Information Handling System (IHS) having a plurality of Central Processing Units (CPUs) to:
measure an operating performance level for each of the plurality of CPUs; and in response to a determination that the operating performance level of any given one of the CPUs does not match a target performance level for all of the CPUs, apply an offset to a voltage regulator measurement associated with the given CPU that causes the operating performance level of the given CPU to match the target performance level for all of the CPUs, wherein the offset is selected to maintain a power consumed by the given CPU within a reporting error band indicated by a manufacturer to the CPU for the operating performance level.

16 . The memory device of claim 15 , wherein the operating performance level of the given CPU is below the target performance level for all of the CPUs, wherein the offset has a negative value that compensates for the IHS's otherwise over reporting of the operating performance level of the given CPU.

17 . The memory device of claim 15 , wherein the operating performance level of the given CPU is above the target performance level for all of the plurality of CPUs, and wherein the offset has a positive value that compensates for the IHS's otherwise under reporting of the operating performance level of the given CPU.

18 . In an Information Handling System (IHS) having a plurality of Central Processing Units (CPUs), a method comprising:
measuring an operating performance level for each of the plurality of CPUs; and in response to a determination that the operating performance level of any given one of the CPUs does not match a target performance level for all of the CPUs, applying an offset to a voltage regulator measurement associated with the given CPU that causes the operating performance level of the given CPU to match the target performance level for all of the CPUs, wherein the offset is selected to maintain a power consumed by the given CPU within a reporting error band indicated by a manufacturer to the CPU for the operating performance level.

19 . The method claim 18 , wherein the operating performance level of the given CPU is below the target performance level for all of the CPUs, wherein the offset has a negative value that compensates for the IHS's otherwise over reporting of the operating performance level of the given CPU.

20 . The method claim 18 , wherein the operating performance level of the given CPU is above the target performance level for all of the plurality of CPUs, and wherein the offset has a positive value that compensates for the IHS's otherwise under reporting of the operating performance level of the given CPU.

Assignees

• Dell Products Lp

Inventors

• Jenne John Erven
• Khatri Mukund P

Classifications

• G06F11/3409

  for performance assessment · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title

• G06F9/44505 Primary

  Configuring for program initiating, e.g. using registry, configuration files · CPC title