Bandwidth Efficient Method for Generating an Alpha Hint Buffer

Patent metadata

Field	Value
Publication number	US-2017213315-A1
Application number	US-201615242478-A
Country	US
Kind code	A1
Filing date	Aug 19, 2016
Priority date	Jan 22, 2016
Publication date	Jul 27, 2017
Grant date	—

Abstract

A graphics processing unit (GPU) renders graphical objects into a group of pixels and stores the pixels in an on-chip buffer on the same chip as the GPU. Each pixel has an alpha value that indicates transparency of the pixel. The GPU reads the alpha value of each pixel from the on-chip buffer. According to alpha values of the group of pixels, the GPU generates an alpha hint in the system memory for the group of pixels. The alpha hint represents an aggregate of the alpha values of the group of pixels. The GPU then stores the group of pixels into a frame buffer in the system memory.

First claim

What is claimed is:

1 . A method for generating an alpha hint in a system memory to reduce memory access, the method comprising:
rendering, by a graphical processing unit (GPU), graphical objects into a group of pixels stored in an on-chip buffer on a same chip as the GPU; reading an alpha value of each pixel from the on-chip buffer, the alpha value indicating transparency of the pixel; generating the alpha hint in the system memory for the group of pixels according to alpha values of the group of pixels, the alpha hint representing an aggregate of the alpha values; and storing the group of pixels into a frame buffer in the system memory.

2 . The method of claim 1 , further comprising:
executing, by a fragment shader, shader codes to read the alpha value and to generate the alpha hint.

3 . The method of claim 2 , further comprising:
executing a list of commands including a number of draw calls and the draw hint command.

4 . The method of claim 1 , wherein the alpha hint is a binary value that indicates at least whether the group of pixels are all fully-transparent and whether the group of pixels are all fully-opaque.

5 . The method of claim 1 , wherein generating the alpha hint further comprises:
setting a first bit of the alpha hint when a pixel in the group is fully-transparent; and keeping the first bit set for the group of pixels.

6 . The method of claim 1 , wherein generating the alpha hint further comprises:
setting a second bit of the alpha hint when a pixel in the group is fully-opaque; and keeping the second bit set for the group of pixels.

7 . The method of claim 1 , wherein generating the alpha hint further comprises:
concurrently setting different bits of the alpha hint according to the alpha values of two or more pixels in the group.

8 . The method of claim 1 , wherein generating the alpha hint further comprises:
performing atomic OR operations to serialize write access to the alpha hint.

9 . The method of claim 1 , wherein generating the alpha hint further comprises:
performing, for each pixel in the group, an atomic OR operation on a current value of the alpha hint and a binary mask determined from the alpha value of the pixel.

10 . The method of claim 1 , further comprising:
rendering a next group of pixels concurrently with generating the alpha hint in the system memory.

11 . A graphics device for generating an alpha hint in a system memory to reduce memory access, the graphics device comprising:
an on-chip buffer; and rendering hardware to render graphical objects into a group of pixels and store the group of pixels in the on-chip buffer, wherein the rendering hardware is further operative to:
read an alpha value of each pixel from the on-chip buffer, the alpha value indicating transparency of the pixel,
generate the alpha hint in the system memory for the group of pixels according to alpha values of the group of pixels, the alpha hint representing an aggregate of the alpha values, and
store the group of pixels into a frame buffer in the system memory.

12 . The graphics device of claim 11 , wherein the rendering hardware includes a fragment shader operative to execute shader codes to read the alpha value and to generate the alpha hint.

13 . The graphics device of claim 12 , wherein the rendering hardware is further operative to execute a list of commands including a number of draw calls and the draw hint command.

14 . The graphics device of claim 11 , wherein the alpha hint is a binary value that indicates at least whether the group of pixels are all fully-transparent and whether the group of pixels are all fully-opaque.

15 . The graphics device of claim 11 , wherein the rendering hardware is further operative to set a first bit of the alpha hint when a pixel in the group is fully-transparent, and to keep the first bit set for the group of pixels.

16 . The graphics device of claim 11 , wherein the rendering hardware is further operative to set a second bit of the alpha hint when a pixel in the group is fully-opaque, and to keep the second bit set for the group of pixels.

17 . The graphics device of claim 11 , wherein the rendering hardware is further operative to concurrently set different bits of the alpha hint according to the alpha values of two or more pixels in the group.

18 . The graphics device of claim 11 , wherein the rendering hardware is further operative to perform atomic OR operations to serialize write access to the alpha hint.

19 . The graphics device of claim 11 , wherein the rendering hardware is further operative to perform, for each pixel in the group, an atomic OR operation on a current value of the alpha hint and a binary mask determined from the alpha value of the pixel.

20 . The graphics device of claim 11 , wherein the rendering hardware is further operative to render a next group of pixels concurrently with generation of the alpha hint in the system memory.

Assignees

• Mediatek Inc

Inventors

• Chen Ying-Chieh
• Lu I-Hsuan
• Lin Shih-Chin

Classifications

• G06T11/40 Primary

  Filling planar surfaces by adding surface attributes, e.g. adding colours or textures · CPC title

• G06T11/60

  Creating or editing images; Combining images with text · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title