Signal driver slew rate control

Patent metadata

Field	Value
Publication number	US-2017201243-A1
Application number	US-201615000214-A
Country	US
Kind code	A1
Filing date	Jan 19, 2016
Priority date	Jan 12, 2016
Publication date	Jul 13, 2017
Grant date	—

Abstract

An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (i) generate a plurality of delayed signals each as a copy of an input signal shifted in time by a sequence of respective delays based on a control signal and (ii) change a number of driver signals that are active during each delay in the sequence of respective delays based on the input signal and the plurality of delayed signals to control a slew rate of an output signal. The second circuit may be configured to drive the output signal in response to the driver signals.

First claim

1 . An apparatus comprising:
a first circuit configured to (i) generate a plurality of delayed signals each as a copy of an input signal shifted in time by a sequence of respective delays based on a control signal and (ii) change a number of driver signals that are active during each delay in said sequence of respective delays based on said input signal and said plurality of delayed signals to control a slew rate of an output signal; and a second circuit configured to drive said output signal in response to said driver signals, wherein an initial delay in said sequence of respective delays has a fixed duration that maintains said slew rate of said output signal at a constant rate until said output signal crosses a threshold voltage.

2 . The apparatus according to claim 1 , wherein said first circuit comprises (i) a plurality of delay cells connected in series and configured to generate said plurality of delayed signals and (ii) a pre-driver circuit configured to (a) receive all of said input signal and said delayed signals and (b) generate said driver signals based on all of said input signal and said delayed signals.

3 . The apparatus according to claim 1 , wherein said first circuit is further configured to (i) deactivate a first majority of said driver signals that are active within a first few delays at a beginning of said sequence of respective delays, (ii) activate none to a few of said driver signals that are inactive within said first few delays at said beginning of said sequence of respective delays, and (iii) activate a second majority of said driver signals that are inactive within a second few delays at an end of said sequence of respective delays.

4 . The apparatus according to claim 1 , wherein (i) a first number of driver signals that are activated is different than a second number of said driver signals that deactivated in one or more first delays in said sequence of respective delays and (ii) a third number of said driver signals that are active during one or more second delays in said sequence of respective delays is less than a total number of said driver signals.

5 . The apparatus according to claim 1 , wherein said first circuit is further configured to have at most ten percent of said driver signals active to drive said output signal to opposite voltage levels concurrently during said sequence of respective delays.

6 . The apparatus according to claim 1 , wherein at least one subsequent delay after said initial delay in said sequence of respective delays has a programmable duration that adjusts said slew rate of said output signal after said output signal has crossed said threshold voltage.

7 . The apparatus according to claim 1 , wherein said input signal is an address signal or a command signal received by a command/address bus of a double data rate (DDR) memory module.

8 . The apparatus according to claim 7 , wherein said DDR memory module comprises a double data rate fourth generation (DDR4) dual in-line memory module (DIMM).

9 . The apparatus according to claim 1 , wherein (i) each delay in said sequence of respective delays except said initial delay has a first programmable duration controlled by said control signal over a range of durations and (ii) said apparatus further comprises a third circuit configured to generate said input signal by delaying a clock signal by a second programmable duration.

10 . The apparatus according to claim 9 , wherein said second programmable duration is inversely related to said first programmable duration to maintain a constant delay from said clock signal said output signal over said range of durations as controlled by said control signal.

11 . The apparatus according to claim 9 , wherein said third circuit comprises a plurality of delay cells arranged in series.

12 . The apparatus according to claim 1 , wherein said apparatus implements a registered clock driver (RCD) circuit.

13 . The apparatus according to claim 12 , wherein said RCD circuit is at least double data rate fourth generation (DDR4) compliant.

14 . The apparatus according to claim 1 , wherein said output signal addresses a plurality of dynamic random access memory (DRAM) chips.

15 . The apparatus according to claim 1 , wherein said number of driver signals that are active during each delay in said sequence of respective delays is based on a selected one of three or more slew rate settings.

16 . A method for signal driver slew rate control, comprising the steps of:
generating a plurality of delayed signals each as a copy of an input signal shifted in time by a sequence of respective delays based on a control signal; changing a number of driver signals that are active during each delay in said sequence of respective delays based on said input signal and said plurality of delayed signals to control said slew rate of an output signal; and driving said output signal in response to said driver signals, wherein an initial delay in said sequence of respective delays has a fixed duration that maintains said slew rate of said output signal at a constant rate until said output signal crosses a threshold voltage.

17 . An apparatus comprising:
a first circuit configured to (i) generate a trim signal based on a fabrication process parameter of said apparatus and (ii) generate a control signal that determines a slew rate of an output signal based on both said trim signal and a target signal, wherein said target signal provides a programmable offset to said trim signal; and a second circuit configured to drive said output signal at said slew rate in response to an input signal.

18 . The apparatus according to claim 17 , wherein said second circuit comprises:
a third circuit configured to (i) generate a plurality of delayed signals each as a copy of said input signal shifted in time by a sequence of respective delays based on said control signal, and (ii) change a number of driver signals that are active during each delay in said sequence of respective delays based on said input signal and said plurality of delayed signals to control said slew rate of said output signal; and a fourth circuit configured to drive said output signal in response to said driver signals.

19 . The apparatus according to claim 17 , wherein (i) said first circuit is further configured to generate a sense frequency indicative of said fabrication process parameter and (ii) said trim signal is one of a plurality of slew rate settings selected in response to said sense frequency.

20 . The apparatus according to claim 17 , wherein said first circuit comprises an adder configured to generate said control signal as a sum of said trim signal and said target signal.

Assignees

• Integrated Device Tech

Inventors

• Hu Zhigang
• Yu Hui
• Wang Shaokang
• Zhang Yuan
• Yu Yue

Classifications

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• H03K5/15 Primary

  Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors (distributing, switching or gating arrangements H03K17/00) · CPC title