Non-volatile memory with efficient programming

Patent metadata

Field	Value
Publication number	US-2017200501-A1
Application number	US-201614994525-A
Country	US
Kind code	A1
Filing date	Jan 13, 2016
Priority date	Jan 13, 2016
Publication date	Jul 13, 2017
Grant date	—

Abstract

A non-volatile memory system includes a plurality of NAND strings (or other arrangements) that form a monolithic three dimensional memory structure, bit lines, word lines, and one or more control circuits. Multiple NAND strings of the plurality of NAND strings have different select gates connected to different select lines. The multiple NAND strings are connected to a common bit line. The multiple NAND strings are connected to a common word line via their respective different select gates. The one or more control circuits concurrently program multiple memory cells on the multiple NAND strings.

First claim

1 . An apparatus, comprising:
a bit line; a word line; multiple non-volatile memory cells connected to both the bit line and the word line; and one or more control circuits connected to the memory cells, the one or more control circuits are configured to concurrently program the multiple memory cells connected to both the bit line and the word line.

2 . The apparatus of claim 1 , wherein:
the one or more control circuits are configured to concurrently program the multiple memory cells with the same data.

3 . The apparatus of claim 2 , further comprising:
additional memory cells connected to the bit line and the word line, the one or more control circuits are configured to program the additional memory cells with different data at a different time than programming the multiple memory cells.

4 . The apparatus of claim 1 , wherein:
the one or more control circuits are configured to concurrently program the multiple memory cells with pseudo data.

5 . The apparatus of claim 1 , further comprising:
a common data store, the one or more control circuits are configured to concurrently program the multiple memory cells with data stored in the common data store.

6 . The apparatus of claim 1 , further comprising:
select gates connected to the bit line, the select gates are positioned between the bit line and the multiple memory cells, each memory cell of the multiple memory cells are connected to and access the bit line via a different select gate.

7 . The apparatus of claim 1 , wherein:
the one or more control circuits are configured to verify the programming separately for each of the multiple memory cells.

8 . The apparatus of claim 1 , wherein:
the one or more control circuits are configured to concurrently verify the programming for all of the multiple memory cells.

9 . An apparatus, comprising:
a bit line; a word line; a plurality of non-volatile memory cells arranged as multiple vertical NAND strings that are part of a three dimensional memory structure, the plurality of non-volatile memory cells includes multiple non-volatile memory cells directly connected to the word line, each of the multiple memory cells are in a different NAND string that includes a separate select gate that is directly connected to the bit line and a separate select line such that each of the multiple memory cells are connected to the bit line via a respective separate select gate; and one or more control circuits connected to the memory cells, the one or more control circuits are configured to concurrently program the multiple memory cells that are directly connected to the word line and connected to the bit line via respective separate select gates.

10 . The apparatus of claim 9 , wherein:
the multiple NAND strings are part of a block of memory; and the one or more control circuits are configured to program a portion of the block with real data, the one or more control circuits are configured to pad a remaining portion of the block with pseudo data by the concurrently programming of the multiple memory cells.

11 . The apparatus of claim 10 , wherein:
the pseudo data is a pattern of all zeroes; and the one or more control circuits are selected from the group consisting of a controller and a state machine.

12 . The apparatus of claim 1 , wherein:
the plurality of non-volatile memory cells are part of a monolithic three dimensional memory structure.

13 . A method comprising:
simultaneously programming a plurality of non-volatile memory cells connected to a common bit line and a common word line, the simultaneously programming the plurality of memory cells includes simultaneously programming memory cells on different NAND strings that are part of a three dimensional memory array, the different NAND strings are connected to the common bit line and are in a common block.

14 . The method of claim 13 , wherein:
the simultaneously programming includes loading data into a latch and simultaneously programming the plurality of non-volatile memory cells based on the data in the latch.

15 . The method of claim 13 , wherein:
the simultaneously programming includes programming pseudo data into the plurality of memory cells.

16 . The method of claim 15 , further comprising:
programming real data into additional memory cells connected to the common bit line and the common word line subsequent to simultaneously programming.

17 . The method of claim 13 , further comprising:
simultaneously verifying the plurality of memory cells.

18 . (canceled)

19 . The method of claim 13 , wherein
the common word line connects to all NAND strings in the common block; each NAND string includes at least one select gate; and the simultaneously programming memory cells on different NAND strings includes turning on the at least one select gate for each of the different NAND strings.

20 . An apparatus, comprising:
a memory interface circuit configured to communicate with a managing circuit for a three dimensional array of non-volatile memory cells; and a control circuit connected to the memory interface circuit, the control circuit is configured to instruct the managing circuit to enable select gates for multiple memory cells connected to both of a pair of control lines, the select gates connect the memory cells to a first control line of the pair of control lines, the control circuit is configured to transmit common data to the managing circuit for programming of the multiple memory cells, the control circuit is configured to transmit a command to the managing circuit to concurrently program the multiple memory cells with the common data.

21 . The apparatus of claim 20 , wherein:
the control circuit is configured to instruct the managing circuit to concurrently verify programming of the multiple memory cells.

22 . An apparatus, comprising:
a bit line; a physical word line; a plurality of NAND strings connected to the bit line and the physical word line, the NAND strings are part of a three dimensional memory structure; and means for concurrently programming the plurality of NAND strings via the physical word line.

Assignees

• Sandisk Technologies Inc

Inventors

• Yang Nian Niles
• Avila Chris

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title