Image sensor with flexible interconnect capabilities

Patent metadata

Field	Value
Publication number	US-2017195587-A1
Application number	US-201715464068-A
Country	US
Kind code	A1
Filing date	Mar 20, 2017
Priority date	Sep 21, 2011
Publication date	Jul 6, 2017
Grant date	—

Abstract

Electronic devices may include image sensors having configurable image sensor pixel interconnections. Image sensors may include image sensor pixels coupled to analog circuitry via configurable interconnect circuitry. The analog circuitry may include many analog circuit blocks. The analog circuit blocks may control and read out signals from associated image sensor pixels. The configurable interconnect circuitry may be controlled to reroute the connections between the analog circuit blocks and specific groups of image sensor pixels. Digital circuitry may be coupled to the analog circuitry via configurable interconnect circuitry. The digital circuitry may include digital circuit blocks. There may be significantly more image pixels controlled by a small number of analog circuit blocks, which are in turn controlled by a smaller number of digital circuit blocks. The image sensor pixel array, the configurable interconnect circuitry, the analog circuitry, and the digital circuitry may be vertically stacked.

First claim

What is claimed is:

1 . A method of operating an image sensor comprising first and second groups of image pixels, wherein the image sensor is coupled to a plurality of control circuits, the method comprising:
generating image signals using the first and second groups of image pixels; routing signals from a selected control circuit of the plurality of control circuits to a selected one of the first and second groups of image pixels using configurable interconnect circuitry; and routing the image signals generated by the first group of image pixels to an additional selected control circuit of the plurality of control circuits using the configurable interconnect circuitry.

2 . The method defined in claim 1 , further comprising:
receiving selector bits at control inputs of an address generating multiplexer; receiving pixel address bits corresponding to a given pixel in the selected one of the first and second groups of image pixels at data inputs of the address generating multiplexer; and using the address generating multiplexer to output a selected pixel address bit of the pixel address bits based on the selector bits.

3 . The method defined in claim 2 , further comprising:
receiving the selected pixel address bit at logic circuitry; and using the logic circuitry to output a selection signal based on the pixel address bit.

4 . The method defined in claim 3 , wherein receiving the selected pixel address bit at the logic circuitry comprises:
receiving the selected pixel address bit at inverting circuitry.

5 . The method defined in claim 3 , wherein receiving the selected pixel address bit at the logic circuitry comprises:
receiving the selected pixel address bit at an input of an XOR gate.

6 . The method defined in claim 3 , wherein routing signals from the selected control circuit to the selected group of image pixels comprises:
receiving the selection signal from the logic circuitry at control inputs of a control signal routing multiplexer; receiving pixel control signals from the plurality of control circuits; and using the control signal routing multiplexer to route pixel control signals of the selected control circuit to the selected group of image pixels based on the selection signal.

7 . The method defined in claim 3 , wherein routing the image signals generated by the first group of image pixels to the additional selected control circuit comprises:
receiving the selection signal from the logic circuitry at control inputs of a demultiplexer having outputs coupled to the plurality of control circuits; receiving an image signal from a given pixel in the first group of image pixels at an input of the demultiplexer; and using the demultiplexer to route the image signal from the given pixel to the additional selected control circuit based on the selection signal.

8 . The method defined in claim 1 , further comprising:
routing the image signals generated by the second group of image pixels to the additional selected control circuit, while routing the image signals generated by the first group of image pixels to the additional selected control circuit.

9 . The method defined in claim 1 , further comprising:
routing the image signals generated by the second group of image pixels to the selected control circuit while routing the image signals generated by the first group of image pixels to the additional selected control circuit.

10 . A method of operating an image sensor comprising first and second groups of image pixels arranged in rows and columns, wherein the image sensor is coupled to a plurality of control circuits, the method comprising:
sensing light with the first and second groups of image pixels; selectively routing control signals from a first control circuit of the plurality of control circuits to the first group of image pixels using configurable interconnect circuitry; and selectively routing pixel output signals from the first group of image pixels to a second control circuit of the plurality of control circuits using the configurable interconnect circuitry.

11 . The method defined in claim 10 , wherein the first group of image pixels includes image pixels from at least two adjacent rows.

12 . The method defined in claim 11 , wherein the first group of image pixels includes image pixels from at least two adjacent columns.

13 . The method defined in claim 10 , wherein the control signals are selectively routed from the first control circuit to the first group of image pixels during a first time period, the method further comprising:
selectively routing additional control signals from a third control circuit of the plurality of control circuits to the second group of image pixels during a second time period that is different than the first time period.

14 . The method defined in claim 10 , further comprising:
receiving selector bits at control inputs of an address generating multiplexer; receiving pixel address bits corresponding to a given pixel in the selected one of the first and second groups of image pixels at data inputs of the address generating multiplexer; and using the address generating multiplexer to output a selected pixel address bit of the pixel address bits based on the selector bits.

15 . The method defined in claim 14 , further comprising:
receiving the selected pixel address bit at logic circuitry; and using the logic circuitry to output a selection signal based on the pixel address bit.

16 . The method defined in claim 15 , wherein selectively routing control signals from the first control circuit to the first group of image pixels further comprises:
receiving the selection signal from the logic circuitry at control inputs of a control signal routing multiplexer; receiving pixel control signals from the plurality of control circuits; and using the control routing multiplexer to route the control signals from the first control circuit to the first group of image pixels based on the selection signal.

17 . An image sensor comprising:
a first group of image pixels that generates image signals and that is coupled to a plurality of control circuits; a second group of image pixels that generates image signals and that is coupled to the plurality of control circuits; and configurable interconnect circuitry that routes signals from a selected control circuit of the plurality of control circuits to a selected one of the first and second groups of image pixels, and that routes the image signals generated by the first group of image pixels to an additional selected control circuit of the plurality of control circuits.

18 . The image sensor defined in claim 17 , wherein the configurable interconnect circuitry comprises:
an address generating multiplexer having control inputs at which selector bits are received, and having data inputs at which pixel address bits corresponding to a given pixel in the selected one of the first and second groups of pixels are received, wherein the address generating multiplexer outputs a selected pixel address bit of the pixel address bits based on the selector bits.

19 . The image sensor of claim 18 , wherein the configurable interconnect circuitry further comprises:
logic circuitry that receives the selected pixel address bit from the address generating multiplexer, and that outputs a selection signal based on the pixel address bit.

20 . The image sensor of claim 19 , wherein the configurable interconnect circuitry further comprises:
a control signal routing multiplexer that

Assignees

• Semiconductor Components Ind Llc

Inventors

• Kirsch Graham

Classifications

• H04N25/71

  Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors · CPC title

• H04N25/79

  Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors · CPC title

• H04N25/40 Primary

  Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled · CPC title

• H04N25/772

  comprising A/D, V/T, V/F, I/T or I/F converters · CPC title

• H04N25/44 Primary

  by partially reading an SSIS array · CPC title