Stacked nanowire semiconductor device

Patent metadata

Field	Value
Publication number	US-2017194431-A1
Application number	US-201715396842-A
Country	US
Kind code	A1
Filing date	Jan 3, 2017
Priority date	Jan 5, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a stack of nanowires, the stack including:
a first nanowire having a first length;
a second nanowire having a second length, the second nanowire arranged above the first nanowire; and
a third nanowire having a third length, the third nanowire arranged above the second nanowire; and
a gate stack arranged over channel regions of the first nanowire, the second nanowire, and the third nanowire.

2 . The device of claim 1 , wherein the first nanowire has a length greater than a length of the second nanowire.

3 . The device of claim 1 , further comprising:
a third nanowire having a third length, the third nanowire arranged above the second nanowire, wherein the gate stack is arranged over channel regions of the first nanowire, the second nanowire, and the third nanowire

4 . The device of claim 3 , wherein the second nanowire has a length greater than a length of the third nanowire.

5 . The device of claim 3 , further comprising a source/drain region contacting the first, second, and third nanowires.

6 . The device of claim 3 , further comprising:
a first source/drain region arranged on the first nanowire; a second source/drain region arranged on the second nanowire; and a third source/drain region arranged on the third nanowire.

7 . The device of claim 3 , wherein the first nanowire, the second nanowire, and the third nanowire include a semiconductor material.

Assignees

• IBM

Inventors

• Guillorn Michael A
• Nicoll William L
• Wang Hanfei

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H01L29/0673 Primary

  Electricity · mapped topic

• H01L29/42384

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L29/41733

  Electricity · mapped topic