Fan-out multi-chip package and its fabricating method

Patent metadata

Field	Value
Publication number	US-2017194293-A1
Application number	US-201615245653-A
Country	US
Kind code	A1
Filing date	Aug 24, 2016
Priority date	Dec 31, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

A fan-out multi-chip package has a first redistribution layer and a plurality of chips encapsulated in an encapsulant. A dielectric layer and a second redistribution layer are formed on the encapsulant. A bottom surface of the encapsulant is formed when forming the encapsulant. The first redistribution layer has a plurality of connecting surfaces exposed on the bottom surface of the encapsulant. The dielectric layer is formed on the bottom surface of the encapsulant without covering the connecting surfaces. The second redistribution layer includes a plurality of bump pads coupled to the connecting surfaces. The fan-out circuitry is covered by the dielectric layer. Thereby, a multi-chip package is able to reduce possible damages to the active surfaces and bonding pads of the chips during packaging process.

First claim

What is claimed is:

1 . A fan-out multi-chip package, comprising:
a plurality of chips stacked on each other in a staggered stack arrangement; a first redistribution layer formed on a periphery of the plurality of chips, the first redistribution layer having a plurality of first connecting points electrically connected to the plurality of chips and a plurality of connecting surfaces; an encapsulant Ruined to encapsulate the plurality of chips and the first redistribution layer, the encapsulant having a bottom surface, wherein the bottom surface, the plurality of connecting surfaces of the first redistribution layer, and a back surface of one of the plurality of chips are coplanar to each other and forms a carrier plane; a second redistribution layer formed on the carrier plane, the second redistribution layer being electrically connected to the first redistribution layer; and a dielectric layer formed on the carrier plane and configured to cover the second redistribution layer.

2 . The package as claimed in claim 1 , further comprising a plurality of metal wires encapsulated by the encapsulant and configured to electrically connect the plurality of chips to the first connecting points.

3 . The package as claimed in claim 1 , wherein the plurality of chips has a first chip adjacent to a second chip, the second chip being laterally displaced from the first chip, and the second chip being stacked above the first chip without covering bond pads of the first chip.

4 . The package as claimed in claim 1 , wherein the plurality of chips has a plurality of first chips and a plurality of second chips, the plurality of first chips and the plurality of second chips are stacked to be alternating from one another, the plurality of first chips are vertically aligned to each other, and the plurality of second chips are vertically aligned to each other.

5 . The package as claimed in claim 4 , wherein when a first chip of the plurality of first chips is stacked on top of a second chip of the plurality of second chips, bond pads of the second chip is not covered by the first chip.

6 . The package as claimed in claim 4 , wherein when a second chip of the plurality of second chips is stacked on top of a first chip of the plurality of firstchips, bond pads of the first chip is not covered by the second chip.

7 . The package as claimed in claim 1 , further comprising a plurality of solder balls protruding from the dielectric layer and electrically connected to the second redistribution layer.

8 . The package as claimed in claim 1 , further comprising a protective plate stacked on an active surface of one of the plurality of chips.

9 . The package as claimed in claim 1 , further comprising a plurality of die attach layers, each of the plurality of die attach layers is formed between two chips of the plurality of chips.

10 . The package as claimed in claim 1 , wherein the back surface of one of the chips is completely covered by the dielectric layer.

11 . A fabricating method of a fan-out multi-chip package, comprising:
providing a temporary carrier, the temporary carrier having a carrier plane; forming a first redistribution layer on the carrier plane of the temporary carrier, the first redistribution layer having a plurality of first connecting points and a plurality of connecting surfaces; stacking a plurality of chips on carrier plane of the temporary carrier in a staggered stack arrangement, wherein the plurality of chips are electrically connected to the plurality of first connecting points; forming an encapsulant on the carrier plane to encapsulate the chips and the first redistribution layer, the encapsulant having a bottom surface defined by the carrier plane, wherein the bottom surface, the plurality of connecting surfaces of the first redistribution layer, and a back surface of one of the plurality of chips are coplanar to each other; removing the temporary carrier to expose the connecting surfaces, the bottom surface of the encapsulant and a back surface of the chips; and forming a dielectric layer and a second redistribution layer on the bottom surface of the encapsulant, wherein the second redistribution layer is electrically connected to the first redistribution layer and the dielectric layer is configured to cover the second redistribution layer.

12 . The method as claimed in claim 11 , further comprising:
forming a plurality of metal wires to electrically connect the chips to the first connecting points.

13 . The method as claimed in claim 11 , wherein the plurality of chips has a first chip adjacent to a second chip, the second chip being laterally displaced from the first chip, and the second chip being stacked above the first chip without covering bond pads of the first chip.

14 . The method as claimed in claim 11 , wherein the plurality of chips has a plurality of first chips and a plurality of second chips, the plurality of first chips and the plurality of second chips are stacked to be alternating from one another, the plurality of first chips are vertically aligned to each other, and the plurality of second chips are vertically aligned to each other.

15 . The method as claimed in claim 14 , wherein when a first chip of the plurality of first chips is stacked on top of a second chip of the plurality of second chips, bond pads of the second chip is not covered by the first chip.

16 . The method as claimed in claim 14 , wherein when a second chip of the plurality of second chips is stacked on top of a first chip of the plurality of firstchips, bond pads of the first chip is not covered by the second chip.

17 . The method as claimed in claim 11 , further comprising:
performing singulation process to form a plurality of individual fan-out multi-chip packages.

18 . The method as claimed in claim 11 , further comprising:
forming a plurality of solder balls protruding from the dielectric layer and electrically connected to the second redistribution layer.

19 . The method as claimed in claim 11 , further comprising:
disposing a protective plate on an active surface of one of the plurality of chips.

20 . The method as claimed in claim 11 , further comprising:
disposing a plurality of die attach layers, each of the plurality of die attach layers is disposed between two chips of the plurality of chips.

Assignees

• Powertech Technology Inc

Inventors

• Chang Chia-Wei
• Lin Kuo-Ting

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/075

  of bond wires · CPC title