Low Power Sense Amplifier For A Flash Memory System

Patent metadata

Field	Value
Publication number	US-2017194055-A1
Application number	US-201615371496-A
Country	US
Kind code	A1
Filing date	Dec 7, 2016
Priority date	Dec 31, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

Multiple embodiments of a low power sense amplifier for use in a flash memory system are disclosed. In some embodiments, the loading on a sense amplifier can be adjusted by selectively attaching one or more bit lines to the sense amplifier, where the one or more bit lines each is coupled to an extraneous memory cell.

First claim

What is claimed is:

1 . A flash memory system, comprising:
a first circuit comprising a selected flash memory cell to be read and a first bit line, wherein during a read operation the first bit line is discharged through the selected flash memory cell; a second circuit comprising a reference flash memory cell and a second bit line, wherein during a read operation the second bit line is discharged through the reference flash memory cell; a timing comparison circuit for outputting a first value when the voltage of the first bit line drops below a voltage threshold before the voltage of the second bit line during a read operation and for outputting a second value when the voltage of the second bit line drops below the voltage threshold before the voltage of the first bit line during a read operation, wherein the first value and second value each indicate a value stored in the selected flash memory cell.

2 . The flash memory system of claim 1 , wherein the timing comparison circuit comprises a flip-flop.

3 . The flash memory system of claim 1 , wherein the timing comparison circuit comprises two inverters and two NAND gates.

4 . The flash memory system of claim 1 , wherein the first bit line and second bit line are charged prior to a read operation.

5 . The flash memory system of claim 1 , wherein the selected flash memory cell is coupled to the timing comparison circuit during a read operation by a multiplexor.

6 . The flash memory system of claim 5 , wherein the reference flash memory cell is coupled to the timing comparison circuit during a read operation by a multiplexor.

7 . A flash memory system, comprising:
a first array of flash memory cells, the first array comprising a selected flash memory cell; a second array of flash memory cells; a third array of flash memory cells, the third array comprising a reference memory cell; a fourth array of flash memory cells; a sense amplifier coupled to the selected flash memory cell and to a programmable number of flash memory bit lines in the second array; and a reference sense amplifier coupled to the reference memory cell and to a programmable number of flash memory bit lines in the fourth array; wherein a value stored in the selected flash memory cell is determined using the selected flash memory cell and the reference memory cell.

8 . The flash memory system of claim 7 , wherein the sense amplifier is coupled to a programmable number of flash memory bit lines in the second array through a programmable number of multiplexors.

9 . The flash memory system of claim 9 , wherein the reference sense amplifier is coupled to a programmable number of flash memory bit lines in the fourth array through a programmable number of multiplexors.

Assignees

• Silicon Storage Tech Inc

Inventors

• Qian Xiaozhou
• Pi Xiao Yan
• Yue Kai Man
• Rao Qing
• Bian Lisa

Classifications

• G11C2207/2254

  Calibration · CPC title

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title

• G11C29/50

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G11C16/24 Primary

  Bit-line control circuits · CPC title