Display device, source drive integrated circuit, timing controller and driving method thereof

Patent metadata

Field	Value
Publication number	US-2017193892-A1
Application number	US-201615381440-A
Country	US
Kind code	A1
Filing date	Dec 16, 2016
Priority date	Dec 31, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

Provided are a display device and a driving method thereof. Each source drive integrated circuit (IC) of the display device includes a first random signal generator configured to generate a first random signal, a delay unit configured to generate first and second Source Output Enable (SOE) signals by randomly delaying an SOE signal in response to the first random signal, a first output group configured to output a data voltage at a first timing in response to the first internal SOE signal, and a second output group configured to output a data voltage at a second timing in response to the second internal SOE signal. The present disclosure utilizes a random signal generator to randomly disperse timings of SOE signals temporally and spatially within a source drive IC or between source drive ICs, thereby minimizing the peak current.

First claim

What is claimed is:

1 . A display device, comprising:
a display panel in which data lines and gate lines are intersecting each other and pixels are arranged in a matrix; a first source drive integrated circuit (IC) and a second source drive integrated circuit (IC) configured to supply a data voltage to the data lines of the display panel in response to a Source Output Enable (SOE) signal; and a timing controller configured to transmit data of an input image and the SOE signal to the first source drive IC, and the second source drive IC, wherein each of the first source drive IC and the second source drive IC comprises:
a first random signal generator configured to generate a first random signal;
a delay unit configured to randomly delay the SOE signal in response to the first random signal to generate a first internal SOE signal and a second internal SOE signal;
a first output group configured to output the data voltage at a first timing in response to the first internal SOE signal; and
a second output group configured to output the data voltage at a second timing in response to the second internal SOE signal.

2 . The display device of claim 1 , wherein the timing controller comprises:
a second random signal generator configured to generate a second random signal; and a signal generator configured to, in response to the second random signal, randomly delay a reference source output signal to generate a first SOE signal for controlling an output timing of the first source drive IC and a second SOE signal for controlling an output timing of the second source drive IC.

3 . The display device of claim 2 , wherein at least one of the first and second random signal generators comprises a Linear Feedback Shift Register (LFSR).

4 . The display device of claim 3 , wherein at least one of the delay unit and the signal generator comprises:
a multiplexer configured to, in response to an output signal of the LFSR, select any one of clocks whose phases are sequentially delayed; and a flipflop configured to, in response to a clock received from the multiplexer, output latched input data to output the first and second internal SOE signals.

5 . The display device of claim 4 , further comprising a switch array disposed between the first random signal generator and the multiplexer, wherein the switch array periodically or randomly changes a signal transmission path between the first random signal generator and the multiplexer.

6 . The display device of claim 4 , further comprising a switch array disposed between the second random signal generator and the multiplexer, wherein the switch array periodically or randomly changes a signal transmission path between the second random signal generator and the multiplexer.

7 . A source drive Integrated Circuit (IC), comprising:
a random signal generator configured to generate a random signal; a delay unit configured to randomly delay a Source Output Enable (SOE) signal in response to the random signal to generate a first internal SOE signal and a second internal SOE signal; a first output group configured to output a first data voltage at a first timing in response to the first internal SOE signal; and a second output group configured to output a second data voltage at a second timing in response to the second internal SOE signal.

8 . The source drive IC of claim 7 , wherein the random signal generator comprises a Linear Feedback Shift Register (LFSR).

9 . The source drive IC of claim 8 , wherein the delay unit comprises:
a multiplexer configured to, in response to an output signal of the LFSR, select any one of clocks whose phases are sequentially delayed; and a flipflop configured to, in response to a clock received from the multiplexer, output latched input data to output the SOE signals.

10 . The source drive IC of claim 9 , further comprising a switch array disposed between the random signal generator and the multiplexer, wherein the switch array periodically or randomly changes a signal transmission path between the random signal generator and the multiplexer.

11 . A timing controller of a display device, comprising:
a random signal generator configured to generate a random signal; and a signal generator configured to, in response to the random signal, randomly delay a reference source output signal to generate a first Source Output Enable (SOE) signal for controlling an output timing of a first source drive integrated circuit (IC) and a second SOE signal for controlling an output timing of a second source drive IC.

12 . The timing controller of claim 11 , wherein the random signal generator comprises a Linear Feedback Shift Register (LFSR).

13 . The timing controller of claim 12 , wherein the signal generator comprises:
a multiplexer configured to, in response to an output signal of the LFSR, select any one of clocks whose phases are sequentially delayed; and a flipflop configured to, in response to a clock received from the multiplexer, output latched input data to output the first and second SOE signals.

14 . The timing controller of claim 13 , further comprising a switch array disposed between the random signal generator and the multiplexer, wherein the switch array periodically or randomly changes a signal transmission path between the random signal generator and the multiplexer.

15 . A driving method of a display device, comprising:
generating a first random signal; in response to the first random signal, randomly delaying a Source Output Enable (SOE) signal to generate a first internal SOE signal and a second internal SOE signal; and controlling an output timing of a first output group within a first source drive Integrated Circuit (IC) in response to the first internal SOE signal, and controlling an output timing of a second output group within the first source drive IC in response to the second internal SOE signal.

16 . The driving method of claim 15 , further comprising:
generating a second random signal; and in response to the second random signal, randomly delaying a reference source output signal to generating a first SOE signal for controlling an output timing of the first source drive IC and a second SOE signal for controlling a second source drive IC.

Assignees

• Lg Display Co Ltd

Inventors

• Ha Sungchul

Classifications

• G09G2330/06

  Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3688

  suitable for active matrices only · CPC title

• G09G2330/025

  Reduction of instantaneous peaks of current · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title