Methods and systems for vector length management

Patent metadata

Field	Value
Publication number	US-2017193351-A1
Application number	US-201514984955-A
Country	US
Kind code	A1
Filing date	Dec 30, 2015
Priority date	Dec 30, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

An apparatus includes a state machine lattice. The apparatus also includes a memory. The memory of the apparatus is configured to receive an event vector, such that the event vector includes an indication of a result of data analysis using the state machine lattice. The apparatus further includes a control system. The control system of the apparatus is configured to selectively provide only a portion of the event vector.

First claim

What is claimed is:

1 . An apparatus, comprising:
a state machine lattice; a memory configured to receive an event vector, wherein the event vector includes an indication of a result of data analysis using the state machine lattice; and a control system configured to selectively provide only a portion of the event vector.

2 . The apparatus of claim 1 , further comprising an event buffer and wherein the control system is configured to cause the portion of the event vector to be provided to the event buffer.

3 . The apparatus of claim 1 , further comprising a host, wherein the control system is configured to cause the portion of the event vector to be provided to the host.

4 . The apparatus of claim 1 , wherein the portion corresponds to a region of the memory.

5 . The apparatus of claim 1 , wherein the portion comprises a subset of bits of the event vector.

6 . The apparatus of claim 1 , wherein the portion comprises a subset of bits stored in a region of the memory.

7 . The apparatus of claim 1 , wherein the portion comprises a plurality of portions of the event vector, wherein each portion of the plurality of portions corresponds to a respective subset of elements of the state machine lattice.

8 . The apparatus of claim 7 , wherein the control system is configured to cause the portion to be provided only when then portion indicates a match occurred as the indication of a result.

9 . The apparatus of claim 7 , wherein the control system is configured to cause an indication to be provided when the portion indicates that no match occurred as the indication of a result.

10 . An apparatus, comprising:
a memory configured to:
receive an event vector comprising an indication of a result of data analysis of a data stream by a state machine engine comprising elements; and
store the event vector across regions of the memory, wherein the regions correspond to subsets of the elements of the state machine engine, wherein the indication of the result is stored in a first region corresponding to a first subset of the elements that generated the result.

11 . The apparatus of claim 10 , comprising an event vector control system configured to initiate the transmission of data from the first region to an event buffer.

12 . The apparatus of claim 11 , wherein the event vector control system is configured to determine whether an indication of a second result of the data analysis is present in a second region corresponding to a second subset of the elements that generated the second result.

13 . The apparatus of claim 12 , wherein the event vector control system is configured to transmit the indication of the second result to the event buffer when the event vector control system determines that the indication of the second result is present in the second region.

14 . The apparatus of claim 12 , wherein the event vector control system is configured to transmit a null indication to the event buffer when the event vector control system determines that the indication of the second result is not present in the second region.

15 . The apparatus of claim 10 , comprising an event vector control system configured to initiate the transmission of the event vector to an event buffer.

16 . The apparatus of claim 10 , comprising a host configured to selectively retrieve portions of the event vector from the event buffer, wherein the portion includes the indication of the result.

17 . An apparatus, comprising:
a state machine engine, comprising:
an event buffer; and
an event vector control system configured to:
retrieve an indication of an occurrence of a result of data analysis of a data stream by one state machine element of a plurality of state machine elements of a state machine engine from an event vector stored in a event vector memory; and
provide the indication of the occurrence of the result to the event buffer.

18 . The apparatus of claim 17 , wherein the event vector control system is configured to transmit, to the event buffer, the indication of the occurrence of the result in conjunction with all data stored in a region of the event vector memory having the indication of the occurrence of the result.

19 . The apparatus of claim 18 , wherein the event vector control system is configured to determine whether an indication of an occurrence of a second result of the data analysis of the data stream by a second one state machine element of the plurality of state machine elements of the state machine engine is present in the event vector memory.

20 . The apparatus of claim 19 , wherein the event vector control system is configured to transmit, to the event buffer, the indication of the occurrence of the second result to the event buffer in conjunction with all data stored in a second region of the event vector memory having the indication of the occurrence of the second result.

21 . The apparatus of claim 17 , wherein the event vector control system is configured to transmit the event vector to the event buffer, wherein the event vector comprises values of each state of the plurality of elements of the state machine engine.

22 . An apparatus, comprising:
an event vector control system configured to:
selectively transmit one out of every n-bits of a portion of an event vector stored in an event vector memory to an event buffer, wherein the event vector comprises respective values related to a state of each of a plurality of elements in a state machine engine, wherein the respective values each comprise an indication of whether a result of data analysis of a data stream by one element of the plurality of elements occurred.

23 . The apparatus of claim 22 , wherein the event vector control system is configured to selectively transmit one out of every n-bits of all remaining portions of the event vector stored in the event vector memory to the event buffer.

24 . The apparatus of claim 23 , wherein the event vector control system is configured to selectively transmit the one out of every n-bits of all remaining portions of the event vector to the event buffer based on a control signal.

25 . The apparatus of claim 22 , wherein event vector control system is configured to selectively transmit the one out of every n-bits of a second portion of the event vector to the event buffer, wherein the second portion of the event vector corresponds to a second portion of the state machine engine.

26 . The apparatus of claim 25 , wherein the event vector control system is configured to selectively transmit the one out of every n-bits of the second portion of the event vector based on a control signal.

27 . An apparatus, comprising:
a host; a bus interface coupled to the host; an event buffer coupled to the bus interface; and an event vector control system configured to:
retrieve an indication of an occurrence of a result of data analysis of a data stream by at least one state machine element of a plurality of state machine elements of a state machine engine from an event vector stored in an event vector memory; and
transmit the indication of the occurrence of the result to the event buffer.

28 . The apparatus of claim 27 , wherein the event vector control system is configured to transmit the indication as part of transmission of the event vector, as part of transmission of one out of every n-bits of the event vector, as part of t

Assignees

• Micron Technology Inc

Inventors

• Noyes Harold B
• Brown David R
• Glendenning Paul
• Dlugosch Paul D

Classifications

• G06N5/02

  Knowledge representation; Symbolic representation · CPC title

• G06K9/00973

  Physics · mapped topic

• G06N3/04 Primary

  Architecture, e.g. interconnection topology · CPC title

• G06K9/6219

  Physics · mapped topic

• G06V10/94 Primary

  Hardware or software architectures specially adapted for image or video understanding · CPC title