Protecting Data Memory in a Signal Processing System

Patent metadata

Field	Value
Publication number	US-2017192847-A1
Application number	US-201514985851-A
Country	US
Kind code	A1
Filing date	Dec 31, 2015
Priority date	Dec 31, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.

First claim

What is claimed is:

1 . A signal processing system comprising:
a data memory component configured to store values corresponding to signal processing of at least one digital signal; a plurality of parity bits associated with the data memory component, the plurality of parity bits including a set of group parity bits for each group of memory words of a plurality of groups of memory words in the data memory component; a processor coupled to receive the at least one digital signal, the processor configured to perform the signal processing of the at least one digital signal and to check the plurality of parity bits for a memory error; and a parity management component coupled to the plurality of parity bits and coupled to receive an address of a memory word in the data memory component and a value read from or written to the memory word by the processor during the signal processing, the parity management component configured to update group parity bits in the plurality of parity bits corresponding to the address of the memory word based on the value.

2 . The signal processing system of claim 1 , in which the plurality of groups are non-overlapping groups of memory words in which a single soft error can affect only one memory word per group.

3 . The signal processing system of claim 1 , in which the signal processing is configured to write and read each memory word of a plurality of memory words of the data memory such that for each write of a value to a memory word of the plurality of memory words, group parity bits corresponding to a group of the memory word are updated based on the value and a single read of the value from the memory word is performed in which the group parity bits are updated based on the value.

4 . The signal processing system of claim 3 , in which the parity management component is coupled to receive a parity enable flag indicating whether or not parity updates are enabled, and in which the signal processing is configured to manage a value of the parity enable flag to ensure that for each write of a value to a memory word with parity updates enabled, a single read of the value from the memory word is performed with parity updates enabled.

5 . The signal processing system of claim 1 , in which the signal processing system is a radar system and the at least one digital signal is a plurality of digital intermediate frequency (IF) signals generated by a plurality of receive channels of the radar system, each receive channel configured to receive a reflected signal from transmission of a frame of chirps and to generate a digital IF signal of samples of the reflected signal.

6 . The signal processing system of claim 5 , in which the signal processing is configured to:
write first values corresponding to the plurality of digital IF signals into a plurality of memory words in the data memory, in which, for each memory word of the plurality of memory words, the parity management component updates the group parity bits in the plurality of parity bits corresponding to a group of the memory word based on a value written in the memory word; and read the first values from the plurality of memory words, in which, for each memory word of the plurality of memory words, the parity management component updates the group parity bits corresponding to the group of the memory word based on a value read from the memory word.

7 . The signal processing system of claim 6 , in which the signal processing is configured to:
write second values corresponding to the plurality of digital IF signals into the plurality of memory words in the data memory, in which for each memory word in the plurality of memory words, group parity bits corresponding to the group of the memory word are updated based on a value written into the memory word; read the second values from the plurality of memory words, in which for each memory word in the plurality of memory words, the group parity bits corresponding to the group of the memory word are updated based on a value read from the memory word; and perform signal processing on the second values to generate the first values.

8 . The signal processing system of claim 1 , in which each set of group parity bits consists of a parity bit for each bit position of a memory word.

9 . The signal processing system of claim 1 , in which each set of group parity bits consists of P parity bits for each bit position of a memory word, in which a value of P depends on a number of words N in a group.

10 . The signal processing system of claim 9 , in which the value of P is chosen as a smallest value that satisfies N>2 P −P−1.

11 . The signal processing system of claim 9 , in which the parity management component is configured to determine a subset of group parity bits corresponding to a memory word of a group based on ordinality of the memory word in the group.

12 . The signal processing system of claim 11 , in which the parity management component includes a parity identification circuit configured to determine the subset of group parity bits corresponding to a memory word of a group, the parity identification circuit including:
a first component coupled to receive a binary representation of the ordinality of the memory word, the first component configured to output a first binary representation of an index of a left most non-zero bit of the binary representation of the ordinality; a first adder coupled to the first component to receive the first binary representation and coupled to receive the binary representation of the ordinality, the first adder configured to output a second binary representation of a sum of the first binary representation and the binary representation of the ordinality; a second component coupled to the first adder to receive the second binary representation, the second component configured to output a third binary representation of an index of a left most non-zero bit of the second binary representation; and a second adder coupled to the second component to receive the third binary representation and coupled to receive the binary representation of the ordinality, the second adder configured to output a fourth binary representation of a sum of the third binary representation and the binary representation of the ordinality.

13 . A method for data memory protection in a signal processing system, the method comprising:
dividing memory words of a data memory of the signal processing system into a plurality of groups, in which a plurality of parity bits associated with the data memory includes a set of group parity bits for each group of the plurality of groups; performing signal processing on a least one digital signal, in which each memory word of a plurality of memory words of the data memory is written and read such that for each write of a value to a memory word of the plurality of memory words, group parity bits corresponding to a group of the memory word are updated based on the value and a single read of the value from the memory word is performed in which the group parity bits are updated based on the value; and determining whether a soft error has occurred based on the plurality of parity bits.

14 . The method of claim 13 , in which the plurality of groups are non-overlapping groups of memory words in which a single soft error can affect only one memory word per group.

15 . The method of claim 14 , in which each set of group parity bits consists of a parity bit for each bit position of a memory word.

16 . The method of claim 14 , in which each set of group parity bits consists of P parity bits for each bit position of a memory wor

Assignees

• Texas Instruments Inc

Inventors

• Rao Sandeep
• Ramasubramanian Karthik
• Ginsburg Brian Paul

Classifications

• G06F3/064

  Management of blocks · CPC title

• G01S13/34

  using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal · CPC title

• G01S13/583

  using transmission of continuous unmodulated waves, amplitude-, frequency-, or phase-modulated waves and based upon the Doppler effect resulting from movement of targets · CPC title

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G01S7/352

  Receivers · CPC title