High-speed pseudo-random bit sequence (prbs) pattern generator, error detector and error counter

Patent metadata

Field	Value
Publication number	US-2017192830-A1
Application number	US-201514986347-A
Country	US
Kind code	A1
Filing date	Dec 31, 2015
Priority date	Dec 31, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

High-speed PRBS-N pattern generator, error detector and error counter circuits are provided that have relatively simple circuit configurations, that quickly synchronize and align the input data with the generated pattern, that easily and quickly detect the occurrence of a bit shifting event, and that quickly resynchronize and realign the input data with the generated pattern after a bit shifting event has occurred. The error counter may be implemented with low-speed circuitry even though the pattern generator and error detector operate at the same speed as the high-speed input data signal. This reduces the complexity and power consumption of the error counter.

First claim

What is claimed is:

1 . A pseudo-random binary sequence (PRBS) pattern generator, error detector and counter circuit comprising:
an input data port that receives a multi-bit input data signal; a PRBS pattern generator that is electrically coupled to the input data port; an error detector electrically coupled to the input data port, the error detector detecting if mismatches occur between bits output from the PRBS pattern generator and respective bits of the multi-bit input data signal received at the input data port, wherein the error detector outputs an output signal from an output node thereof having a state that indicates whether or not a mismatch has been detected; and a controller and error counter electrically coupled to the error detector and to the PRBS pattern generator, the controller and error counter outputting a control signal to the PRBS pattern generator to cause the PRBS pattern generator to either enter an initialization mode of operations or a comparison mode of operations, wherein during the initialization mode of operations, N bits of the multi-bit input data signal are loaded into the PRBS pattern generator, where N is a number of bits in a PRBS pattern, and wherein during the comparison mode of operations, the error detector detects if mismatches occur between bits output from the PRBS pattern generator and respective bits of the multi-bit input data signal, and wherein the controller and error counter counts the number of mismatches that are detected.

2 . The PRBS pattern generator, error detector and counter circuit of claim 1 , wherein the controller and error counter operates at a lower rate than a data rate of the multi-bit input data signal.

3 . The PRBS pattern generator, error detector and counter circuit of claim 2 , wherein the controller and error counter operates at a lower rate than a rate at which the PRBS pattern generator operates.

4 . The PRBS pattern generator, error detector and counter circuit of claim 1 , wherein during the comparison mode of operations, the controller and error counter determines a bit error rate (BER) corresponding to the number of mismatches that have occurred over time and compares the BER to a first predetermined threshold level to determine whether the PRBS pattern generator needs to be reinitialized.

5 . The PRBS pattern generator, error detector and counter circuit of claim 4 , wherein if the controller and error counter determines that the PRBS pattern generator needs to be reinitialized, the controller and error counter switches the PRBS pattern generator, error detector and error counter circuit from the comparison mode of operations to the initialization mode of operations to cause the PRBS pattern generator to be reinitialized by loading N bits of the multi-bit input data signal into the PRBS pattern generator.

6 . The PRBS pattern generator, error detector and counter circuit of claim 5 , wherein after the controller and error counter has caused the PRBS pattern generator to be reinitialized, the controller and error counter causes the PRBS pattern generator, error detector and error counter circuit to exit the initialization mode of operations and re-enter the comparison mode of operations.

7 . The PRBS pattern generator, error detector and counter circuit of claim 1 , wherein the PRBS pattern generator comprises:
a shift register comprising N registers, each register having an input node, an output node and a clock signal node; a first modulo-2 (mod-2) adder employed in the shift register in between an output node of a first register of the N registers and an input node of a second register of the N registers, the first mod-2 adder having first and second input nodes and an output node; and a switch employed in the shift register in between the output node of the first mod-2 adder and the input node of the second register, the switch having first and second input nodes, an output node and a control node, the first input node of the switch being connected to the output node of the first mod-2 adder, the second input node of the switch being connected to the input data port.

8 . The PRBS pattern generator, error detector and counter circuit of claim 7 , wherein the error detector comprises:
a second mod-2 adder having first and second input nodes and an output node, the first input node of the second mod-2 adder being connected to the input data port for receiving the multi-bit input data signal, the second input node of the second mod-2 adder being connected to the output node of the first mod-2 adder for receiving an output signal outputted from the first mod-2 adder; and an error trigger having a set node, a clear node and an output node, the set node of the error trigger being connected to the output node of the second mod-2 adder, and wherein an input node of the controller and error counter is connected to the output node of the error trigger, and wherein a first output node of the controller and error counter is connected to the control node of the switch.

9 . The PRBS pattern generator, error detector and counter circuit of claim 8 , wherein the controller and error counter causes the PRBS pattern generator, error detector and error counter circuit to enter the initialization mode of operations by outputting a deasserted control signal to the control node of the switch to cause the switch to connect the second input node of the switch to the output node of the switch such that the multi-bit input data signal is applied to the input node of the second register, wherein the initialization mode of operations continues until a clock signal received at the clock signal nodes of the registers has caused N bits of the multi-bit input data signal to be shifted into the N registers, respectively.

10 . The PRBS pattern generator, error detector and counter circuit of claim 9 , wherein the initialization mode of operations aligns the N-bit PRBS pattern produced by the PRBS pattern generator with the multi-bit input data signal.

11 . The PRBS pattern error detector and counter of claim 9 , wherein the controller and error counter operates at a lower frequency than a frequency of the clock signal received at the clock signal nodes of the registers.

12 . The PRBS pattern generator, error detector and counter circuit of claim 9 , wherein the controller and error counter causes the PRBS pattern generator, error detector and error counter circuit to exit the initialization mode of operations and enter the comparison mode of operations by outputting an asserted control signal to the control node of the switch to cause the switch to connect the first input node of the switch to the output node of the switch such that bit values contained in the respective registers are shifted through the shift register as the clock signal received at the clock signal nodes of the registers clocks the registers, and wherein during the comparison mode of operations, the first mod-2 adder performs an exclusive OR operation on a bit output from the first register and a bit output from a third register of the N registers to produce an output bit of the PRBS pattern generator at the output node of the first mod-2 adder, and wherein during the comparison mode of operations, the second mod-2 adder performs an exclusive OR operation on the output bit of the PRBS pattern generator and a bit of the multi-bit input data signal to produce an output bit of the second mod-2 adder, and wherein the output bit of the second mod-2 adder is received at the set node of the error trigger.

13 . The PRBS pattern generator, error detector and counter circuit of claim 12 , wherein if the output bit of the second mod-2 ad

Assignees

• Avago Technologies General Ip

Inventors

• Bai Dezhao
• Chaahoub Faouzi

Classifications

• G06F11/076 Primary

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F7/584

  using finite field arithmetic, e.g. using a linear feedback shift register · CPC title

• G06F2207/581

  Generating an LFSR sequence, e.g. an m-sequence; sequence may be generated without LFSR, e.g. using Galois Field arithmetic · CPC title

• H03K3/84 Primary

  Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators · CPC title

• G06F11/0709

  in a distributed system consisting of a plurality of standalone computer nodes, e.g. clusters, client-server systems · CPC title