Providing task-triggered determinisitic operational mode for simultaneous multi-threaded superscalar processor

Patent metadata

Field	Value
Publication number	US-2017192790-A1
Application number	US-201614988964-A
Country	US
Kind code	A1
Filing date	Jan 6, 2016
Priority date	Jan 6, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

A task identifier-based mechanism is configured to temporarily disable a dual-issue capability of one or more threads in a superscalar simultaneous multi-threaded core. The core executes a first thread and a second thread which are each provided with a dual-issue capability wherein up to two instructions may be issued in parallel. In response to a task identifier being received that is indicative of a task requiring an improved level of determinism, the dual-issue capability of at least one of the first thread or the second thread is temporarily disabled.

First claim

What is claimed is:

1 . A method comprising:
executing a first thread and a second thread, wherein the first thread is provided with a dual-issue capability such that up to two instructions of the first thread are issued in parallel, and wherein the second thread is provided with a dual-issue capability such that up to two instructions of the second thread are issued in parallel; receiving a task identifier indicative of a task that requires an improved level of determinism; and in response to the task identifier, disabling the dual-issue capability of at least one of the first thread or the second thread.

2 . The method of claim 1 , wherein the first thread and the second thread are simultaneously executed on a simultaneous multi-threaded superscalar processor.

3 . The method of claim 1 , wherein the disabling of the dual-issue capability of at least one of the first thread or the second thread is performed until the task is completed.

4 . The method of claim 1 , wherein the disabling of the dual-issue capability of at least one of the first thread or the second thread is set to a duration of at least N clock cycles, N being a positive integer greater than three.

5 . The method of claim 1 , wherein the disabling of the dual-issue capability of at least one of the first thread or the second thread is set to a duration of time that is defined using an N-bit saturating counter, and wherein the N-bit saturating counter is configured to accumulate a count indicative of how many consecutive instruction issue slots are not filled with an instruction from at least one of the first thread or the second thread.

6 . The method of claim 5 , wherein the duration of time expires when the N-bit saturating counter saturates.

7 . An apparatus comprising:
a processor configured for executing a first thread and a second thread, wherein the first thread is provided with a dual-issue capability such that up to two instructions of the first thread are issued in parallel, and wherein the second thread is provided with a dual-issue capability such that up to two instructions of the second thread are issued in parallel; and a memory operatively coupled to the processor for storing a task identifier that is indicative of an improved level of determinism being required for a task; wherein the processor is configured for retrieving the task identifier from the non-transitory computer readable memory device and, in response thereto, disabling the dual-issue capability of at least one of the first thread or the second thread.

8 . The apparatus of claim 7 , wherein the processor comprises a simultaneous multi-threaded superscalar processor.

9 . The apparatus of claim 7 , wherein the processor disables the dual-issue capability of at least one of the first thread or the second thread until the task is completed.

10 . The apparatus of claim 7 , wherein the processor sets the disabling of the dual-issue capability of at least one of the first thread or the second thread to a duration of at least N clock cycles, N being a positive integer greater than three.

11 . The apparatus of claim 7 , further comprising an N-bit saturating counter operatively coupled to the processor, wherein the processor sets the disabling of the dual-issue capability of at least one of the first thread or the second thread to a duration of time that is defined using the N-bit saturating counter, and wherein the N-bit saturating counter is configured to accumulate a count indicative of how many consecutive instruction issue slots are not filled with an instruction from at least one of the first thread or the second thread.

12 . The apparatus of claim 11 , wherein the duration of time expires when the N-bit saturating counter saturates.

13 . The apparatus of claim 7 , wherein the apparatus is provided in the form of one or more integrated circuits.

14 . A non-transitory computer readable memory encoded with a computer program comprising computer readable instructions recorded thereon for execution of a method that includes:
executing a first thread and a second thread, wherein the first thread is provided with a dual-issue capability such that up to two instructions of the first thread are issued in parallel, and wherein the second thread is provided with a dual-issue capability such that up to two instructions of the second thread are issued in parallel; receiving a task identifier that is indicative of an improved level of determinism being required for a task and, in response thereto, temporarily disabling the dual-issue capability of at least one of the first thread or the second thread.

15 . The non-transitory computer readable memory of claim 14 , further including instructions for simultaneously executing the first thread and the second thread on a simultaneous multi-threaded superscalar processor.

16 . The non-transitory computer readable memory of claim 14 , further including instructions for using the task identifier to disable the dual-issue capability of at least one of the first thread or the second thread until the task is completed.

17 . The non-transitory computer readable memory of claim 14 , further including instructions for using the task identifier to disable the dual-issue capability of at least one of the first thread or the second thread for a duration of at least N clock cycles, N being a positive integer greater than three.

18 . The non-transitory computer readable memory of claim 14 , further including instructions for using the task identifier to disable the dual-issue capability of at least one of the first thread or the second thread for a duration of time that is defined using an N-bit saturating counter, wherein the N-bit saturating counter is configured to accumulate a count indicative of how many consecutive instruction issue slots are not filled with an instruction from at least one of the first thread or the second thread.

19 . The non-transitory computer readable memory of claim 18 , further including instructions wherein the duration of time expires when the N-bit saturating counter saturates.

Assignees

• Robertson Alistair Paul
• Scobie James Andrew Collier
• Freescale Semiconductor Inc

Inventors

• Robertson Alistair Paul
• Scobie James Andrew Collier

Classifications

• G06F9/3836 Primary

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3009

  Thread control instructions · CPC title

• G06F9/3851 Primary

  from multiple instruction streams, e.g. multistreaming · CPC title