Systems, Apparatuses, and Methods for Aggregate Gather and Stride

Patent metadata

Field	Value
Publication number	US-2017192782-A1
Application number	US-201514984132-A
Country	US
Kind code	A1
Filing date	Dec 30, 2015
Priority date	Dec 30, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

Embodiments of systems, apparatuses, and methods for aggregate gather and scatter are disclosed. In some embodiments, a decoder to decode an instruction, wherein the instruction to include fields for an index of memory address locations, an immediate, and a starting destination register operand and identifier of additional destination registers; and execution circuitry to execute the decoded instruction to gather, from memory at locations indicated by the index of memory locations, data elements and stores them in multiple destination registers in sizes dictated by the immediate are described.

First claim

What is claimed is:

1 . An apparatus comprising:
a decoder to decode an instruction, wherein the instruction to include fields for an index of memory address locations, an immediate, and a starting destination register operand and identifier of additional destination registers; and execution circuitry to execute the decoded instruction to gather, from memory at locations indicated by the index of memory locations, data elements and stores them in multiple destination registers in sizes dictated by the immediate.

2 . The apparatus of claim 1 , wherein the instruction to include an opcode that indicates a size of the data elements to gather.

3 . The apparatus of claim 2 , wherein the size of the data elements to gather is one of 32, 64, 128, or 256-bit.

4 . The apparatus of claim 1 , wherein the identifier of additional destination registers is one of 1, 3, and 7.

5 . The apparatus of claim 1 , wherein the immediate is an 8-bit value.

6 . The apparatus of claim 1 , wherein the instruction to include a writemask operand.

7 . The apparatus of claim 7 , wherein the execution circuitry to store extracted data elements based on values of the writemask operand.

8 . An method comprising:
decoding an instruction, wherein the instruction to include fields for an index of memory address locations, an immediate, and a starting destination register operand and identifier of additional destination registers; and executing the decoded instruction to gather, from memory at locations indicated by the index of memory locations, data elements and stores them in multiple destination registers in sizes dictated by the immediate.

9 . The method of claim 8 , wherein the instruction to include an opcode that indicates a size of the data elements to gather.

10 . The method of claim 9 , wherein the size of the data elements to gather is one of 32, 64, 128, or 256-bit.

11 . The method of claim 8 , wherein the identifier of additional destination registers is one of 1, 3, and 7.

12 . The method of claim 8 , wherein the immediate is an 8-bit value.

13 . The method of claim 8 , wherein the instruction to include a writemask operand.

14 . The method of claim 13 , wherein the extracted data elements are stored based on values of the writemask operand.

15 . A non-transitory machine readable medium storing an instruction, which when executed by a processor to cause the processor to perform a method, the method comprising:
decoding an instruction, wherein the instruction to include fields for an index of memory address locations, an immediate, and a starting destination register operand and identifier of additional destination registers; and executing the decoded instruction to gather, from memory at locations indicated by the index of memory locations, data elements and stores them in multiple destination registers in sizes dictated by the immediate.

Assignees

• Valentine Robert
• Charney Mark J
• Ould-Ahmed-Vall Elmoustapha
• Jha Ashish

Inventors

• Valentine Robert
• Charney Mark J
• Ould-Ahmed-Vall Elmoustapha
• Jha Ashish

Classifications

• G06F9/3016 Primary

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/30109

  having multiple operands in a single register · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F9/30112

  comprising data of variable length · CPC title

• G06F9/30043 Primary

  LOAD or STORE instructions; Clear instruction · CPC title