Systems, Apparatuses, and Methods for Strided Loads

Patent metadata

Field	Value
Publication number	US-2017192781-A1
Application number	US-201514984124-A
Country	US
Kind code	A1
Filing date	Dec 30, 2015
Priority date	Dec 30, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

Detailed herein are systems, apparatuses, and methods for strided loads. In an embodiment, an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields a starting source memory address operand and a starting destination register operand; and execution circuitry to execute the decoded instruction to extract data elements of a defined number of types from contiguous memory beginning at the starting source memory address and, for each type, store the extracted data elements in a packed data register dedicated to that type beginning with starting destination register operand.

First claim

What is claimed is:

1 . An apparatus comprising:
a decoder to decode an instruction, wherein the instruction to include fields a starting source memory address operand and a starting destination register operand; and execution circuitry to execute the decoded instruction to extract data elements of a defined number of types from contiguous memory beginning at the starting source memory address and, for each type, store the extracted data elements in a packed data register dedicated to that type beginning with starting destination register operand.

2 . The apparatus of claim 1 , wherein the instruction to include an opcode indicating the defined number of types.

3 . The apparatus of claim 2 , wherein the defined number of types are two, three, and four.

4 . The apparatus of claim 1 , wherein the defined number of types indicates a number of destination packed data registers.

5 . The apparatus of claim 1 , wherein the instruction to indicate a size of the data elements.

6 . The apparatus of claim 1 , wherein the instruction to include a writemask operand.

7 . The apparatus of claim 7 , the execution circuitry to store extracted data element based on values of the writemask operand.

8 . An method comprising:
decoding an instruction, wherein the instruction to include fields a starting source memory address operand and a starting destination register operand; and executing the decoded instruction to extract data elements of a defined number of types from contiguous memory beginning at the starting source memory address and, for each type, store the extracted data elements in a packed data register dedicated to that type beginning with starting destination register operand.

9 . The method of claim 8 , wherein the instruction to include an opcode indicating the defined number of types.

10 . The method of claim 9 , wherein the defined number of types are two, three, and four.

11 . The method of claim 8 , wherein the defined number of types indicates a number of destination packed data registers.

12 . The method of claim 8 , wherein the instruction to indicate a size of the data elements.

13 . The method of claim 8 , wherein the instruction to include a writemask operand.

14 . The method of claim 8 , wherein the storing of extracted data element is based on values of the writemask operand.

15 . A non-transitory machine readable medium storing an instruction, which when executed causes a processor to perform a method, the method comprising:
decoding an instruction, wherein the instruction to include fields a starting source memory address operand and a starting destination register operand; and executing the decoded instruction to extract data elements of a defined number of types from contiguous memory beginning at the starting source memory address and, for each type, store the extracted data elements in a packed data register dedicated to that type beginning with starting destination register operand.

Assignees

• Valentine Robert
• Ould-Ahmed-Vall Elmoustapha
• Brandt Jason W
• Charney Mark J
• Jha Ashish
• Girkar Milind B
• Toll Bret L
• Stupachenko Evgeny V
• Ostanevich Sergey Y

Inventors

• Valentine Robert
• Ould-Ahmed-Vall Elmoustapha
• Brandt Jason W
• Charney Mark J
• Jha Ashish
• Girkar Milind B
• Toll Bret L
• Stupachenko Evgeny V
• Ostanevich Sergey Y

Classifications

• G06F9/30098

  Register arrangements · CPC title

• G06F9/3016 Primary

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/30038

  using a mask · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30109

  having multiple operands in a single register · CPC title