Information processing apparatus
US-2024385843-A1 · Nov 21, 2024 · US
Systems, Apparatuses, and Methods for Getting Even and Odd Data Elements
US2017192780A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2017192780-A1 |
| Application number | US-201514984078-A |
| Country | US |
| Kind code | A1 |
| Filing date | Dec 30, 2015 |
| Priority date | Dec 30, 2015 |
| Publication date | Jul 6, 2017 |
| Grant date | — |
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Abstract
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Embodiments of systems, apparatuses, and method for getting even or odd data elements are described. For example, in some embodiments, an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields for a first source operand, a second source operand, and a destination operand; and execution circuitry to execute the decoded instruction to extract data elements from even data element positions of the first and second source operands and store the extracted data elements into the destination operand.
First claim
Opening claim text (preview).
What is claimed is: 1 . An apparatus comprising: a decoder to decode an instruction, wherein the instruction to include fields for a first source operand, a second source operand, and a destination operand; and execution circuitry to execute the decoded instruction to extract data elements from even data element positions of the first and second source operands and store the extracted data elements into the destination operand. 2 . The apparatus of claim 1 , wherein the source operands are packed data registers. 3 . The apparatus of claim 1 , wherein the execution circuitry to extract even data elements in parallel. 4 . The apparatus of claim 1 , wherein the execution circuitry to extract even data elements in series. 5 . The apparatus of claim 1 , wherein the instruction to indicate a size of the data elements. 6 . The apparatus of claim 1 , wherein the first source operand is a register and the second source is a memory location. 7 . The apparatus of claim 1 , wherein the data elements extracted from the first source operand are stored in the lower data elements positions of the destination operand. 8 . A method comprising: decoding an instruction, wherein the instruction to include fields for a first source operand, a second source operand, and a destination operand; and executing the decoded instruction to extract data elements from even data element positions of the first and second source operands and store the extracted data elements into the destination operand. 9 . The method of claim 8 , wherein the source operands are packed data registers. 10 . The method of claim 8 , wherein the extracting of even data elements is done in parallel. 11 . The method of claim 8 , wherein the extracting of even data elements is done in series. 12 . The method of claim 8 , wherein the instruction to indicate a size of the data elements. 13 . The method of claim 8 , wherein the first source operand is a register and the second source is a memory location. 14 . The method of claim 8 , wherein the data elements extracted from the first source operand are stored in the lower data elements positions of the destination operand. 18 . A machine readable medium storing instructions, which when executed by a hardware processor cause the processor to perform a method comprising: decoding an instruction, wherein the instruction to include fields for a first source operand, a second source operand, and a destination operand; and executing the decoded instruction to extract data elements from even data element positions of the first and second source operands and store the extracted data elements into the destination operand. 16 . The machine readable medium of claim 15 , wherein the source operands are packed data registers. 17 . The machine readable medium of claim 15 , wherein the extracting of even data elements is done in parallel. 18 . The machine readable medium of claim 15 , wherein the extracting of even data elements is done in series. 19 . The machine readable medium of claim 15 , wherein the first source operand is a register and the second source is a memory location. 20 . The machine readable medium of claim 15 , wherein the data elements extracted from the first source operand are stored in the lower data elements positions of the destination operand.
Assignees
Inventors
Classifications
- G06F9/30032Primary
Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title
Special purpose registers · CPC title
- G06F9/3016Primary
Decoding the operand specifier, e.g. specifier format · CPC title
using a mask · CPC title
Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title
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Frequently asked questions
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- What does patent US2017192780A1 cover?
- Embodiments of systems, apparatuses, and method for getting even or odd data elements are described. For example, in some embodiments, an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields for a first source operand, a second source operand, and a destination operand; and execution circuitry to execute the decoded instruction to extract data element…
- Who is the assignee on this patent?
- Valentine Robert, Ould-Ahmed-Vall Elmoustapha, Brandt Jason W, and 6 more
- What technology area does this patent fall under?
- Primary CPC classification G06F9/30032. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu Jul 06 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).